You copied the Doc URL to your clipboard.

Part A Functional description

Table of Contents

A1 Introduction
A1.1 About the core
A1.2 Features
A1.3 Split/Lock
A1.4 Implementation options
A1.5 Supported standards and specifications
A1.6 Test features
A1.7 Design tasks
A1.8 Product revisions
A2 Technical overview
A2.1 Components
A2.1.1 Instruction fetch
A2.1.2 Instruction decode
A2.1.3 Register rename
A2.1.4 Instruction issue
A2.1.5 Execution pipeline
A2.1.6 L1 data memory system
A2.1.7 L2 memory system
A2.2 Interfaces
A2.3 About system control
A2.4 About the Generic Timer
A3 Clocks, resets, and input synchronization
A3.1 About clocks, resets, and input synchronization
A3.2 Asynchronous interface
A4 Power management
A4.1 About power management
A4.2 Voltage domains
A4.3 Power domains
A4.4 Architectural clock gating modes
A4.4.1 Core Wait for Interrupt
A4.4.2 Core Wait for Event
A4.5 Power control
A4.6 Core power modes
A4.6.1 On
A4.6.2 Off
A4.6.3 Off (emulated)
A4.6.4 Core dynamic retention
A4.6.5 Debug recovery mode
A4.7 Encoding for power modes
A4.8 Power domain states for power modes
A4.9 Power up and down sequences
A4.10 Debug over powerdown
A5 Memory Management Unit
A5.1 About the MMU
A5.1.1 Main functions
A5.1.2 AArch64 behavior
A5.2 TLB organization
A5.2.1 Instruction L1 TLB
A5.2.2 Data L1 TLB
A5.2.3 L2 TLB
A5.3 TLB match process
A5.4 Translation table walks
A5.4.1 AArch64 behavior
A5.5 MMU memory accesses
A5.5.1 Configuring MMU accesses
A5.5.2 Descriptor hardware update
A5.6 Specific behaviors on aborts and memory attributes
A5.6.1 External aborts
A5.6.2 Mis-programming contiguous hints
A5.6.3 Memory attributes
A6 Level 1 memory system
A6.1 About the L1 memory system
A6.1.1 L1 instruction-side memory system
A6.1.2 L1 data-side memory system
A6.2 Cache behavior
A6.2.1 Instruction cache disabled behavior
A6.2.2 Instruction cache speculative memory accesses
A6.2.3 Data cache disabled behavior
A6.2.4 Data cache maintenance considerations
A6.2.5 Data cache coherency
A6.2.6 Write streaming mode
A6.3 L1 instruction memory system
A6.3.1 Program flow prediction
A6.4 L1 data memory system
A6.4.1 Memory system implementation
A6.4.2 Internal exclusive monitor
A6.5 Data prefetching
A6.6 Direct access to internal memory
A6.6.1 Encoding for L1 instruction cache tag, L1 instruction cache data, L1 BTB, L1 GHB, L1 TLB instruction, and BPIQ
A6.6.2 Encoding for L1 data cache tag, L1 data cache data, and L1 TLB data
A6.6.3 Encoding for the L2 unified cache
A6.6.4 Encoding for the L2 TLB
A7 Level 2 memory system
A7.1 About the L2 memory system
A7.2 About the L2 cache
A7.3 Support for memory types
A8 Reliability, Availability, and Serviceability (RAS)
A8.1 Cache ECC and parity
A8.2 Cache protection behavior
A8.3 Uncorrected errors and data poisoning
A8.4 RAS error types
A8.5 Error Synchronization Barrier
A8.6 Error recording
A8.7 Error injection
A9 Generic Interrupt Controller CPU interface
A9.1 About the Generic Interrupt Controller CPU interface
A9.2 Bypassing the CPU interface
A10 Advanced SIMD and floating-point support
A10.1 About the Advanced SIMD and floating-point support
A10.2 Accessing the feature identification registers
A11 Split/Lock
A11.1 Split/Lock implementation in the core
A11.1.1 CPU bridge
A11.1.2 Comparators
A11.1.3 Core RAS reporting signals
A11.1.4 Detectable faults
A11.1.5 Non-detectable faults
A11.1.6 Fault containment
A11.1.7 Fault reaction