ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1
The ID_ISAR3_EL1 provides information about the instruction sets implemented by the core in AArch32.
Bit field descriptions
ID_ISAR3_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Figure B2-53 ID_ISAR3_EL1 bit assignments
- T32EE, [31:28]
Indicates the implemented T32EE instructions:
- TrueNOP, [27:24]
Indicates support for True NOP instructions:
NOPinstructions in both the A32 and T32 instruction sets, and additional NOP-compatible hints.
- T32Copy, [23:20]
Indicates the support for T32 non flag-setting
Support for T32 instruction set encoding T1 of the
MOV(register) instruction, copying from a low register to a low register.
- TabBranch, [19:16]
Indicates the implemented Table Branch instructions in the T32 instruction set.
- SynchPrim, [15:12]
Indicates the implemented Synchronization Primitive instructions:
- SVC, [11:8]
Indicates the implemented SVC instructions:
- SIMD, [7:4]
Indicates the implemented Single Instruction Multiple Data (SIMD) instructions.
USATinstructions, and the Q bit in the PSRs.
UXTB16instructions, and the GE[3:0] bits in the PSRs.
The SIMD field relates only to implemented instructions that perform SIMD operations on the general-purpose registers. In an implementation that supports Advanced SIMD and floating-point instructions, MVFR0, MVFR1, and MVFR2 give information about the implemented Advanced SIMD instructions.
- Saturate, [3:0]
Indicates the implemented Saturate instructions:
QSUBQ bit in the PSRs.
In an AArch64-only implementation, this register is UNKNOWN.
Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR4_EL1, ID_ISAR5_EL1, and ID_ISAR6_EL1. See:
- ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1.
- ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1.
- ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1.
- ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1.
- ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1.
- ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.