SCTLR_EL3, System Control Register, EL3
The SCTLR_EL3 provides top-level control of the system, including its memory system at EL3.
Bit field descriptions
SCTLR_EL3 is a 32-bit register, and is part of the Other system control registers functional group.
This register resets to
Figure B2-77 SCTLR_EL3 bit assignments
- RES0, [31:30]
- RES1, [29:28]
- RES0, [27:26]
- EE, 
Exception endianness. This bit controls the endianness for:
- Explicit data accesses at EL3.
- Stage 1 translation table walks at EL3.
The possible values are:
The reset value is determined by the CFGEND configuration signal.
- I, 
Global instruction cache enable. The possible values are:
Instruction caches disabled. This is the reset value.
Instruction caches enabled.
- C, 
Global enable for data and unifies caches. The possible values are:
Disables data and unified caches. This is the reset value.
Enables data and unified caches.
- M, 
Global enable for the EL3 MMU. The possible values are:
Disables EL3 MMU. This is the reset value.
Enables EL3 MMU.
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.