ICH_VTR_EL2, Interrupt Controller VGIC Type Register, EL2
ICH_VTR_EL2 reports supported GIC virtualization features.
Bit field descriptions
ICH_VTR_EL2 is a 32-bit register and is part of:
- The GIC system registers functional group.
- The Virtualization registers functional group.
- The GIC host interface control registers functional group.
Figure B4-13 ICH_VTR_EL2 bit assignments
- PRIbits, [31:29]
Priority bits. The number of virtual priority bits implemented, minus one.
Priority implemented is 5-bit.
- PREbits, [28:26]
The number of virtual preemption bits implemented, minus one. The value is:
Virtual preemption implemented is 5-bit.
- IDbits, [25:23]
The number of virtual interrupt identifier bits supported. The value is:
Virtual interrupt identifier bits that are implemented is 16-bit.
- SEIS, 
SEI Support. The value is:
The virtual CPU interface logic does not support generation of SEIs.
- A3V, 
Affinity 3 Valid. The value is:
The virtual CPU interface logic supports non-zero values of Affinity 3 in SGI generation System registers.
- nV4, 
Direct injection of virtual interrupts not supported. The value is:
The CPU interface logic supports direct injection of virtual interrupts.
- TDS, 
Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported. The value is:
Implementation supports ICH_HCR_EL2.TDIR.
- RES0, [18:5]
- ListRegs, [4:0]
The number of implemented List registers, minus one.
The core implements 4 list registers. Accesses to ICH_LR_EL2[x] (x>3) in AArch64 are UNDEFINED.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.