ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1
The ID_MMFR3_EL1 provides information about the memory model and memory management support in AArch32.
Bit field descriptions
ID_MMFR3_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Figure B2-60 ID_MMFR3_EL1 bit assignments
- Supersec, [31:28]
Supersections. Indicates support for supersections:
- CMemSz, [27:24]
Cached memory size. Indicates the size of physical memory supported by the core caches:
1TByte or more, corresponding to a 40-bit or larger physical address range.
- CohWalk, [23:20]
Coherent walk. Indicates whether translation table updates require a clean to the point of unification:
Updates to the translation tables do not require a clean to the point of unification to ensure visibility by subsequent translation table walks.
- PAN, [19:16]
Privileged Access Never.
- PAN supported and new
- MaintBcst, [15:12]
Maintenance broadcast. Indicates whether cache, TLB, and branch predictor operations are broadcast:
Cache, TLB, and branch predictor operations affect structures according to shareability and defined behavior of instructions.
- BPMaint, [11:8]
Branch predictor maintenance. Indicates the supported branch predictor maintenance operations.
Supported branch predictor maintenance operations are:
- Invalidate all branch predictors.
- Invalidate branch predictors by MVA.
- CMaintSW, [7:4]
Cache maintenance by set/way. Indicates the supported cache maintenance operations by set/way.
Supported hierarchical cache maintenance operations by set/way are:
- Invalidate data cache by set/way.
- Clean data cache by set/way.
- Clean and invalidate data cache by set/way.
- CMaintVA, [3:0]
Cache maintenance by Virtual Address (VA). Indicates the supported cache maintenance operations by VA.
Supported hierarchical cache maintenance operations by VA are:
Invalidate data cache by VA.
- Clean data cache by VA.
- Clean and invalidate data cache by VA.
- Invalidate instruction cache by VA.
- Invalidate all instruction cache entries.
Must be interpreted with ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR2_EL1, and ID_MMFR4_EL1. See:
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.