ERR0CTLR, Error Record Control Register
The ERR0CTLR contains enable bits for the node that writes to this record:
- Enabling error detection and correction.
- Enabling an error recovery interrupt.
- Enabling a fault handling interrupt.
- Enabling error recovery reporting as a read or write error response.
Bit field descriptions
ERR0CTLR is a 64-bit register and is part of the Reliability, Availability, Serviceability (RAS) registers functional group.
ERR0CTLR resets to CFI , FI , and UI  are UNKNOWN. The rest of the register is RES0.
Figure B3-2 ERR0CTLR bit assignments
- RES0, [63:9]
- CFI, 
Fault handling interrupt for corrected errors enable.
The fault handling interrupt is generated when one of the standard CE counters on ERR0MISC0 overflows and the overflow bit is set. The possible values are:
Fault handling interrupt not generated for corrected errors.
Fault handling interrupt generated for corrected errors.
The interrupt is generated even if the error status is overwritten because the error record already records a higher priority error.
NoteThis applies to both reads and writes.
- RES0, [7:4]
- FI, 
Fault handling interrupt enable.
The fault handling interrupt is generated for all detected Deferred errors and Uncorrected errors. The possible values are:
Fault handling interrupt disabled.
Fault handling interrupt enabled.
- UI, 
Uncorrected error recovery interrupt enable. When enabled, the error recovery interrupt is generated for all detected Uncorrected errors that are not deferred. The possible values are:
Error recovery interrupt disabled.
Error recovery interrupt enabled.
NoteApplies to both reads and writes.
- RES0, 
- ED, 
Error Detection and correction enable. In Lock mode, this bit is RES0. In Split mode, the possible values are:
Error detection and correction disabled.
Error detection and correction enabled.
- This register is accessible from the following registers when ERRSELR.SEL==0: