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Error system register summary

The ERR0* registers are agnostic to the architectural state. For example, this means that for ERRSELR==0 and ERRSELR_EL1==0, ERXPFGFR and ERXPFGFR_EL1 will both access ERR0PFGFR.

For those registers not described in this chapter, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The following table describes the architectural error record registers.

The following table describes the error record registers that are IMPLEMENTATION DEFINED.

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