ICV_CTLR_EL1, Interrupt Controller Virtual Control Register, EL1
ICV_CTLR_EL1 controls aspects of the behavior of the GIC virtual CPU interface and provides information about the features implemented.
Bit field descriptions
ICV_CTLR_EL1 is a 32-bit register and is part of the virtual GIC system registers functional group.
Figure B4-10 ICV_CTLR_EL1 bit assignments
- RES0, [31:16]
- A3V, 
Affinity 3 Valid. The value is:
The virtual CPU interface logic supports non-zero values of Affinity 3 in SGI generation System registers.
- SEIS, 
SEI Support. The value is:
The virtual CPU interface logic does not support local generation of SEIs.
- IDbits, [13:11]
Identifier bits. The value is:
The number of physical interrupt identifier bits supported is 16 bits.
- PRIbits, [10:8]
Priority bits. The value is:
Support 32 levels of physical priority (5 priority bits).
- RES0, [7:2]
- VEOImode, 
Virtual EOI mode. The possible values are:
ICV_EOIR0_EL1 and ICV_EOIR1_EL1 provide both priority drop and interrupt deactivation functionality. Accesses to ICV_DIR_EL1 are UNPREDICTABLE.
ICV_EOIR0_EL1 and ICV_EOIR1_EL1 provide priority drop functionality only. ICV_DIR provides interrupt deactivation functionality.
- VCBPR, 
Common Binary Point Register. Controls whether the same register is used for interrupt preemption of both virtual Group 0 and virtual Group 1 interrupts. The possible values are:
ICV_BPR0_EL1 determines the preemption group for virtual Group 0 interrupts only.
ICV_BPR1_EL1 determines the preemption group for virtual Group 1 interrupts.
ICV_BPR0_EL1 determines the preemption group for both virtual Group 0 and virtual Group 1 interrupts.
Reads of ICV_BPR1_EL1 return ICV_BPR0_EL1 plus one, saturated to 111. Writes to ICV_BPR1_EL1 are ignored.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.