NVIC Registers view
Use the NVIC Registers view to see an alternative view of the registers involved in the NVIC exception/interrupt system.
- The NVIC Registers view is only enabled for Arm®v6-M and Armv7-M architectures.
- You can also use the Registers view to view register information.
The NVIC Registers view updates when registers are changed by the debugger or are manually changed through the command prompt or register view.
Each exception is in one of the following states:
The exception is not active and not pending.
An exception that is being serviced by the processor but has not completed. An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state.
The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending.
- Active and pending
The exception is being serviced by the processor and there is a pending exception from the same source.
Figure 15-36 NVIC Registers view
You can view:
- Current exceptions and interrupts
A table showing the name and status of current exceptions and interrupts.
ID of the exception or interrupt. Entries with an ID of up to, and including, 16 are the system exceptions. The remaining entries are external interrupts extracted from the NVIC_* group of system registers.
NoteThis exact number will vary between platforms.
Name of the exception or interrupt.
Source of the exception or interrupt.
Enabled state of the exception or interrupt. The value 1 indicates True, 0 indicates False, and - indicates not applicable.
Pending state of the exception or interrupt. The value 1 indicates True, 0 indicates False, and - indicates not applicable.
Active state of the exception or interrupt. The value 1 indicates True, 0 indicates False, and - indicates not applicable.
The priority of the exception or interrupt.
- Application Interrupt and Reset Control
Displays the Application Interrupt and Register Control Register (AIRCR) information.
- Interrupt Control State
Displays the Interrupt Control and State Register (ICSR) information.
- Vector Table Offset
Displays the Vector Table Offset Register (VTOR) information.
NoteThe VTOR information is only available for Armv7-M architectures.