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Arm Cortex-M3 DesignStart FPGA-Xilinx edition User Guide : Cortex-M3 processor integration

Cortex®-M3 processor integration

The Cortex®-M3 processor which is included in the Cortex-M3 DesignStart™ FPGA-Xilinx edition deliverables has been pre-integrated with several components to make it easier to use in an FPGA flow.

There are two Tightly Coupled Memory (TCM) instances, for code and data. These are both configurable in size. The Instruction Tightly Coupled Memory (ITCM) can be configured at run time to be aliased to either or both of 0x00000000 and 0x10000000. The Data Tightly Coupled Memory (DTCM) is at a fixed location of 0x20000000.

The instruction code and data code AHB interfaces from the processor are combined internally. Any access from either of these buses which does not match an active ITCM alias is presented on the external instruction AXI interface.

The System AHB (S-AHB) interface from the processor is used to access the DTCM, any accesses which are not within the range of the configured DTCM size are presented on the system AXI interface.

The processor is integrated with a Serial Wire/JTAG Debug Port (SWJ-DP) to provide debug access.

The following figure shows internal memory processing of the instruction code and data code AHB interfaces.

Figure 1-1 Internal memory processing

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