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Arm Cortex-M3 DesignStart FPGA-Xilinx edition User Guide : Flash download requirements

Flash download requirements

The DAPLink processor on the V2C-DAPLink is pre-programmed with a flash download routine. This is used for drag-and-drop programming and debugger code download. To maintain compatibility with the pre-programmed image, you must retain the following components in your system.

Table 5-1 Interface type

Base address Interface path in example design Description
0x00000000 Daplink_if_0/axi_xip_quad_spi_0/AXI_FULL Code execution from dedicated Quad Serial Port Interface (QSPI) on V2C-DAPLink memory interface.
0x40000000 Daplink_if_0/axi_xip_quad_spi_0/AXI_LITE Configuration interface that is used to set QSPI clock polarity and clock phase for eXecute-In-Place (XIP) execution.
0x40020000 daplink_if_0/axi_quad_spi_0 Normal mode QSPI controller used to read, write, and verify code to the dedicated QSPI on the V2C-DAPLink memory interface.
0x40010000 Daplink_if_0/axi_gpio_0 Bit [0] is used to control muxing of the QSPI interface.
0QSPI XIP mode. QSPI is read-only through the axi_xip_quad_spi_0. This is the setting for executing code from the V2C-DAPLink. This is default option.
1QSPI read, write, and verify through the normal mode axi_quad_spi_0 controller.


There is another peripheral, axi_single_spi_0 on the V2C-DAPLink board. This is a normal mode SPI controller that is used to write to the V2C-DAPLink SD card slot. In the example design, this has a base address of 0x40030000. The address of this peripheral is not fixed, however, Arm recommends that you do not change the address unless required.


Bit [0] of axi_gpio_0 must be held LOW while V2C-DAPLink code is executing. If your code must be run from V2C-DAPLink, then you must ensure that your code does not set this signal HIGH.
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