Two constraint files for the example design are included in the
The constraints include internal timing constraints for the Cortex®-M3 processor, particularly asynchronous clock domain crossing paths. These constraints must be included in any design that uses the Cortex-M3 processor. The majority of the I/O connections are made using the board file connections, which automatically populate the I/O pad and I/O voltage standard. The exception is the shield connector, which goes to the V2C-DAPLink adaptor board. This uses a tristate port due to the mix of signal direction. Since this does not map directly onto the board file, the I/O pad and I/O standards for the shield connector are defined in the synthesis constraint file.