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Arm Cortex-M3 DesignStart FPGA-Xilinx edition User Guide : Memory map

Memory map

The following figure shows the memory map of the example Cortex®-M3 DesignStart™ FPGA-Xilinx edition system.

Figure 4-1 Example system memory map


The following table shows the example Cortex-M3 DesignStart FPGA-Xilinx edition memory map.

Table 4-1 Example system memory map

Type Start End Peripheral Instance name Size Comment
Code 0x00000000 0x000FFFFF Instruction Tightly Coupled Memory (ITCM) (lower) Integrated in the Cortex-M3 processor. Configurable Boot region when CFGITCMEN[0] is 1. This indicates that there is no V2C-DAPLink board.
0x00000000 0x000FFFFF Quad Serial Peripheral Interface (QSPI) daplink_if_0/axi-_xip_quad_0 1MB Boot region when CFGITCMEN[0] is 0. This indicates that there is a V2C-DAPLink board. a
0x10000000 0x100FFFFF ITCM (upper) Integrated in the Cortex-M3 processor. 1MB Upper ITCM alias, CFGITCMEN[1] is always HIGH in the example design.
0x10100000 0x1FFFFFFF External - - -
SRAM 0x20000000 0x200FFFFF Data Tightly Coupled Memory (DTCM) Integrated in the Cortex-M3 processor. Configurable eXecute-never (XN) region
0x20100000 0x3FFFFFFF External - - -
Peripheral 0x40000000 0x4000FFFF QSPI eXecute In Place (XIP) daplink_if_0/axi-_xip_quad_0 64KB Provides code execution from QSPI on the V2C-DAPLink board.a
0x40010000 0x4001FFFF GPIO 0 daplink_if_0/axi_gpio_0 64KB Control for QSPI peripheral multiplexer. Bit [0] selects between the two QSPI peripherals.a
0x40020000 0x4002FFFF QSPI daplink_if_0/quad_spi_0 64KB Provides programming control from QSPI on the V2C-DAPLink board.a
0x40030000 0x4003FFFF SPI daplink_if_0/axi-_single_spi_0 64KB Single SPI on a dedicated connector.
0x40040000 0x400FFFFF Unused - - Unused peripheral region
0x40100000 0x4010FFFF UART axi_uartlite_0 64KB Baseboard UART or V2C-DAPLink USB, when fitted.
0x40110000 0x4011FFFF GPIO 1 axi_gpio_0 64KB -
0x40120000 0x4012FFFF GPIO 2 axi_gpio_1 64KB -
0x40130000 0x4013FFFF QSPI axi_quad_spi_0 64KB Provides read/write access to QSPI on V2C-DAPLink board. a
0x40140000 0x5FFFFFFF Unused - - Unused peripheral region.
RAM 0x60000000 0x60001FFF BlockRam axi_bram_ctrl_0 8KB Additional area of RAM. This also supports code execution. a
0x60002000 0x9FFFFFFF Unused - - Unused RAM region.
External device 0xA0000000 0xDFFFFFFF Unused - - Unused external device region.
System 0xE0000000 0xE0000FFF Instrumentation Trace Macrocell (ITM) Integrated in the Cortex-M3 processor. 4KB -
0xE0001000 0xE0001FFF Data Watchpoint and Trace (DWT) Integrated in the Cortex-M3 processor. 4KB -
0xE0002000 0xE0002FFF Flashpatch and Breakpoint (FPB) Integrated in the Cortex-M3 processor. 4KB  
0xE0003000 0xE000DFFF Reserved - - -
0xE000E000 0xE000EFFF System Control Space (SCS) Integrated in the Cortex-M3 processor. 4KB Nested Vectored Interrupt Controller (NVIC), Debug, and system control registers.
0xE000F000 0xE003FFFF Reserved - - -
0xE0040000 0xE0040FFF Trace Port Interface Unit (TPIU) Integrated in the Cortex-M3 processor. 4KB -
0xE0041000 0xE0041FFF Embedded Trace Macrocell (ETM) Integrated in the Cortex-M3 processor. 4KB  
0xE0042000 0xE00FEFFF External PPB - -  
0xE00FF000 0xE0100000 ROM table Integrated in the Cortex-M3 processor. 4KB  
Reserved 0xE0100000 0xFFFFFFFF - - - -

All the AXI peripherals that are detailed in the example design are mapped to either of the following:

  • Peripheral region (0x40000000 to 0x5FFFFFFF).
  • SRAM region (0x60000000 to 0x9FFFFFFF) in the case of the block RAM controller.

If the V2C-DAPLink board is not fitted, then the ITCM RAM, implemented in FPGA memory, is mapped to both 0x00000000 and 0x10000000. Code that is preloaded into the ITCM RAM is executed from address 0x00000000 from boot-up.

If the V2C-DAPLink board is fitted, then the ITCM RAM is only mapped to 0x10000000. For code execution, the V2C-DAPLink board contains a QSPI AXI peripheral configured to eXecute In Place (XIP) mode. This peripheral is named qspi_xip and is mapped to address 0x00000000. Code is executed from this XIP QSPI device on boot-up.

The DTCM is always mapped starting at 0x20000000. In contrast to other Cortex‑M processors, which do not have a TCM, the DTCM is XN.

a The V2C-DAPLink firmware uses this region. Therefore, you must not modify it to retain compatibility with the V2C-DAPLink board.
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