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Arm Cortex-M3 DesignStart FPGA-Xilinx edition User Guide Revision r0p0
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Arm Cortex-M3 DesignStart FPGA-Xilinx edition User Guide : Testbench conditionals
The testbench conditional compilation options are controlled by defines at the top of tb_m3_for_arty_a7.v.
4-3 Conditional compilation options
Set this option if the Quad Serial Port Interface (QSPI) Verilog models have been installed.
Set this option to enable inclusion of the V2C-DAPLink peripherals. Supports lower external stimulus, longer resets, and drivers for Serial Wire Debug (SWD).
If `INCLUDE_DAPLINK option is set, code is normally executed from the V2C-DAPLink QSPI model, and UART output directed to the V2C-DAPLink UART ports. If `DAPLINK_LINK_NF is also set, then code is executed from Instruction Tightly Coupled Memory (ITCM) and UART outputs are directed to the base board UART ports.