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-mcpu

Enables code generation for a specific Arm® processor.

Note

This topic includes descriptions of [ALPHA] and [BETA] features. See Support level definitions.

Syntax

To specify a target processor, use:

-mcpu=name

-mcpu=name[+[no]feature+…] (for architectures with optional extensions)

Where:

name

Specifies the processor.

To view a list of all the supported processors, use:

-mcpu=list

feature

Is an optional architecture feature that might be enabled or disabled by default depending on the architecture or processor.

Note

In general, if an architecture supports the optional feature, then this optional feature is enabled by default. For AArch32 state inputs only, you can use fromelf --decode_build_attributes to determine whether the optional feature is enabled.

+feature enables the feature if it is disabled by default. +feature has no effect if the feature is already enabled by default.

+nofeature disables the feature if it is enabled by default. +nofeature has no effect if the feature is already disabled by default.

Use +feature or +nofeature to explicitly enable or disable an optional architecture feature.

For targets in AArch64 state, you can specify one or more of the following features if the architecture supports it:

  • aes - Cryptographic Extension. See Cryptographic Extensions for more information.
  • crc - CRC extension.
  • crypto - Cryptographic Extension. See Cryptographic Extensions for more information.
  • dotprod - Enables the SDOT and UDOT instructions. Supported in the Armv8.2 and later Application profile architectures, and is optional in Armv8.2 and Armv8.3.
  • fp - Floating-point extension. See Floating-point extensions for more information.
  • fp16 - Armv8.2-A half-precision floating-point extension. See Floating-point extensions for more information.
  • [ALPHA] bf16 - Armv8.6-A BFloat16 floating-point extension. See Floating-point extensions for more information. This extension is optional in Armv8.2 and later Application profile architectures.
  • fp16fml - Half-precision floating-point multiply with add or multiply with subtract extension. Supported in the Armv8.2 and later Application profile architectures, and is optional in Armv8.2-A and Armv8.3-A. See Floating-point extensions for more information.
  • [ALPHA] i8mm, f32mm, f64mm - Armv8.6-A Matrix Multiply extension. This extension is optional in Armv8.2 and later Application profile architectures. See Matrix Multiplication Extension for more information.
  • memtag - Armv8.5-A memory tagging extension. See -fsanitize.
  • profile - Armv8.2-A statistical profiling extension.
  • ras - Reliability, Availability, and Serviceability extension.
  • predres - Enable instructions to prevent data prediction. See Prevention of Speculative execution and data prediction for more information.
  • rcpc - Release Consistent Processor Consistent extension. This extension applies to Armv8.2 and later Application profile architectures.
  • rng - Armv8.5-A random number generation extension.
  • sb - Enable the speculation barrier SB instruction. See Prevention of Speculative execution and data prediction for more information.
  • ssbs - Enable the Speculative Store Bypass Safe instructions. See Prevention of Speculative execution and data prediction for more information.
  • sha2 - Cryptographic Extension. See Cryptographic Extensions for more information.
  • sha3 - Cryptographic Extension. See Cryptographic Extensions for more information.
  • simd - Advanced SIMD extension.
  • sm4 - Cryptographic Extension. See Cryptographic Extensions for more information.
  • sve - Scalable Vector Extension. This extension applies to Armv8 and later Application profile architectures. See Scalable Vector Extension for more information.
  • sve2 - Scalable Vector Extension 2. This extension is part of the early support for Future Architecture Technologies, and applies to Armv8 and later Application profile architectures. See Scalable Vector Extension for more information.
  • tme - Transactional Memory Extension. This extension is part of the early support for Future Architecture Technologies, and applies to Armv8 and later Application profile architectures. See Transactional Memory Extension for more information.

For targets in AArch32 state, you can specify one or more of the following features if the architecture supports it:

  • crc - CRC extension for architectures Armv8 and above.
  • dotprod - Enables the VSDOT and VUDOT instructions. Supported in Armv8.2 and later Application profile architectures, and is optional in Armv8.2 and Armv8.3.
  • dsp - DSP extension for the Armv8‑M.mainline architecture.
  • fp16 - Armv8.2-A half-precision floating-point extension. See Floating-point extensions for more information.
  • [ALPHA] bf16 - Armv8.6-A BFloat16 floating-point extension. See Floating-point extensions for more information. This extension is optional in Armv8.2 and later Application profile architectures.
  • fp16fml - Half-precision floating-point multiply with add or multiply with subtract extension. Supported in the Armv8.2 and later Application profile architectures, and is optional in Armv8.2-A and Armv8.3-A. See Floating-point extensions for more information.
  • [ALPHA] i8mm - Armv8.6-A Matrix Multiply extension. This extension is optional in Armv8.2 and later Application profile architectures. See Matrix Multiplication Extension for more information.
  • mve - MVE extension for the Armv8.1-M architecture profile. See M-profile Vector Extension for more information.
  • ras - Reliability, Availability, and Serviceability extension.
  • sb - Enable the speculation barrier SB instruction. See Prevention of Speculative execution and data prediction for more information.

Note

For targets in AArch32 state, you can use -mfpu to specify the support for floating-point, Advanced SIMD, and Cryptographic Extensions.

Note

To write code that generates instructions for these extensions, use the intrinsics which are described in the Arm® C Language Extensions.

Usage

You can use the -mcpu option to enable and disable specific architecture features.

To disable a feature, prefix with no, for example cortex-a57+nocrypto.

To enable or disable multiple features, chain multiple feature modifiers. For example, to enable CRC instructions and disable all other extensions:

armclang --target=aarch64-arm-none-eabi -mcpu=cortex-a57+nocrypto+nofp+nosimd+crc

If you specify conflicting feature modifiers with -mcpu, the rightmost feature is used. For example, the following command enables the floating-point extension:

armclang --target=aarch64-arm-none-eabi -mcpu=cortex-a57+nofp+fp

You can prevent the use of floating-point instructions or floating-point registers for targets in AArch64 state with the -mcpu=name+nofp+nosimd option. Subsequent use of floating-point data types in this mode is unsupported.

Note

There are no software floating-point libraries for targets in AArch64 state. When linking for targets in AArch64 state, armlink uses AArch64 libraries that contain Advanced SIMD and floating-point instructions and registers. The use of the AArch64 libraries applies even if you compile the source with -mcpu=<name>+nofp+nosimd to prevent the compiler from using Advanced SIMD and floating-point instructions and registers. Therefore, there is no guarantee that the linked image for targets in AArch64 state is entirely free of Advanced SIMD and floating-point instructions and registers.

You can prevent the use of Advanced SIMD and floating-point instructions and registers in images that are linked for targets in AArch64 state. Either re-implement the library functions or create your own library that does not use Advanced SIMD and floating-point instructions and registers.

Default

For targets in AArch64 state (--target=aarch64-arm-none-eabi), the compiler generates generic code for the Armv8‑A architecture in AArch64 state by default.

For targets in AArch32 state (--target=arm-arm-none-eabi), there is no default. You must specify either -march (to target an architecture) or -mcpu (to target a processor).

To see the default floating-point configuration for your processor:

  1. Compile with -mcpu=name -S to generate the assembler file.
  2. Open the assembler file and check that the value for the .fpu directive corresponds to one of the -mfpu options. No .fpu directive implies -mfpu=none.

Cryptographic Extensions

The following table shows which algorithms the cryptographic features include for AArch64 state in the different versions of the Armv8‑A architecture:

Table B1-5 Cryptographic Extensions

Feature Armv8.0‑A Armv8.1‑A Armv8.2‑A Armv8.3‑A Armv8.4‑A and later architectures
+crypto SHA1, SHA256, AES SHA1, SHA256, AES SHA1, SHA256, AES SHA1, SHA256, AES SHA1, SHA256, SHA512, SHA3, AES, SM3, SM4
+aes AES AES AES AES AES
+sha2 SHA1, SHA256 SHA1, SHA256 SHA1, SHA256 SHA1, SHA256 SHA1, SHA256
+sha3 - - SHA1, SHA256, SHA512, SHA3 SHA1, SHA256, SHA512, SHA3 SHA1, SHA256, SHA512, SHA3
+sm4 - - SM3, SM4 SM3, SM4 SM3, SM4

Note

Armv8.0-A refers to the generic Armv8‑A architecture without any incremental architecture extensions. On the armclang command-line, use -march=armv8-a to compile for Armv8.0-A.

For AArch32 state in Armv8‑A and Armv8‑R, if you specify an -mfpu option that includes the cryptographic extension, then the cryptographic extension supports the AES, SHA1, and SHA256 algorithms.

Floating-point extensions

The following table shows the floating-point instructions that are available when you use the floating-point features:

Table B1-6 Floating-point extensions

Feature Armv8.0‑A Armv8.1‑A Armv8.2‑A Armv8.3‑A Armv8.4‑A and later architectures
+fp FP FP FP FP FP
+fp16 - - FP, FP16 FP, FP16 FP, FP16, FP16fml
+fp16fml - - FP, FP16, FP16fml FP, FP16, FP16fml FP, FP16, FP16fml
[ALPHA] +bf16 - - BF16 BF16 BF16

FP refers to the single-precision and double-precision arithmetic operations.

FP16 refers to the Armv8.2-A half-precision floating-point arithmetic operations.

FP16fml refers to the half-precision floating-point multiply with add or multiply with subtract arithmetic operations. These are supported in the Armv8.2 and later Application profile architectures, and are optional in Armv8.2-A and Armv8.3-A.

BF16 refers to the BFloat16 floating-point dot product, matrix multiplication, and conversion operations.

Note

Armv8.0-A refers to the generic Armv8‑A architecture without any incremental architecture extensions. On the armclang command-line, use -march=armv8-a to compile for Armv8.0-A.

Matrix Multiplication Extension

Matrix Multiplication Extension is a component of the Armv8.6-A architecture and is an optional extension for the Armv8.2-A to Armv8.5-A architectures.

The following table shows the options to enable the Matrix Multiplication extension. These options are [ALPHA] support.

Table B1-7 Options for the Matrix Multiplication extension

Feature Description
[ALPHA] +i8mm Enables matrix multiplication instructions for 8-bit integer operations. This also enables the +simd feature in AArch64 state, or Advanced SIMD in AArch32 state.
[ALPHA] +f32mm Enables matrix multiplication instructions for 32-bit single-precision floating-point operations. This also enables the +sve feature in AArch64 state.
[ALPHA] +f64mm Enables matrix multiplication instructions for 64-bit double-precision floating-point operations. This also enables the +sve feature in AArch64 state.

Arm Compiler enables:

  • [ALPHA] Assembly of source code containing Matrix Multiplication instructions.
  • [ALPHA] Disassembly of ELF object files containing Matrix Multiplication instructions.
  • [ALPHA] Support for the ACLE defined Matrix Multiplication intrinsics.

M-profile Vector Extension

M-profile Vector Extension (MVE) is an optional extension for the Armv8.1-M architecture profile.

The following table shows the options to enable MVE.

Table B1-8 Options for the MVE extension

Feature Description
+mve Enables MVE instructions for integer operations.
+mve.fp Enables MVE instructions for integer and single-precision floating-point operations.
+mve.fp+fp.dp Enables MVE instructions for integer, single-precision, and double-precision floating-point operations.

Arm Compiler enables:

  • Assembly of source code containing MVE instructions.
  • Disassembly of ELF object files containing MVE instructions.
  • Support for the ACLE defined MVE intrinsics.
  • [BETA] Automatic vectorization of source code operations into MVE instructions.

Scalable Vector Extension

Scalable Vector Extension (SVE) is a SIMD instruction set for Armv8‑A AArch64, that introduces the following architectural features:

  • Scalable vector length.
  • Per-lane predication.
  • Gather-load and scatter-store.
  • Fault-tolerant speculative vectorization.
  • Horizontal and serialized vector operations.

Arm Compiler enables:

  • Assembly of source code containing SVE instructions.
  • Disassembly of ELF object files containing SVE instructions.

SVE2 builds upon SVE to add many new data-processing instructions that bring the benefits of scalable long vectors to a wider class of applications. To enable SVE2, you must use the +sve2 option.

Transactional Memory Extension

Transactional Memory Extension (TME) is an architecture extension that adds instructions to support lock-free atomic execution of critical sections.

Prevention of Speculative execution and data prediction

Instructions are available to prevent predictions that are based on information gathered from earlier execution within a particular execution context from affecting the later Speculative execution within that context. These instructions are optional for architectures Armv8.0-A to Armv8.4-A, and are mandatory for Armv8.5-A and later architectures. The following features enable these instructions:

  • +predres is available in AArch64 state, and enables the instructions:

    CFP RCTX, Xt
    DVP RCTX, Xt
    CPP RCTX, Xt
  • +sb is available in AArch32 and AArch64 states, and enables the SB instruction.

  • +ssbs is available in AArch64 state, and enables the instructions:

    MRS Xt, SSBS
    MSR SSBS, Xt

Examples

  • To list the processors that target the AArch64 state:

    armclang --target=aarch64-arm-none-eabi -mcpu=list
  • To target the AArch64 state of a Cortex®‑A57 processor:

    armclang --target=aarch64-arm-none-eabi -mcpu=cortex-a57 test.c
  • To target the AArch32 state of a Cortex‑A53 processor, generating A32 instructions:

    armclang --target=arm-arm-none-eabi -mcpu=cortex-a53 -marm test.c
  • To target the AArch32 state of a Cortex‑A53 processor, generating T32 instructions:

    armclang --target=arm-arm-none-eabi -mcpu=cortex-a53 -mthumb test.c
  • To target the AArch32 state of an Arm Neoverse™ N1 processor, use:

    armclang --target=arm-arm-none-eabi -mcpu=neoverse-n1 test.c
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