The meanings of 'TDMI-S', 'JZF-S' and 'T2F-S'
Article ID: 103488165
Published date: 13 Feb 2018
Last updated: -
Applies to: Classic
What do 'TDMI-S', 'JZF-S' and 'T2F-S' stand for?
The ARM7 through ARM11 family processor names carry a variety of suffixes such as those shown in the question.
T : supports both ARM (32-bit) and Thumb (16-bit) instruction sets
An instruction set is a list of binary patterns, or 'opcodes', that represent the different logical operations a processor can perform. Software programs can be written at different levels of abstraction, from low level 'assembly code' where each written instruction typically maps onto one corresponding opcode, up to high-level languages where the written program (source code) needs to be processed by a compiler, which typically converts each written instruction into a whole sequence of opcodes.
ARM processors support one or more instruction sets.
The original ARM instruction set consists of 32-bit opcodes. Therefore, the binary pattern for each possible operation is four bytes long.
To improve code density, a new, smaller instruction set called 'Thumb' was developed, implementing the more commonly used parts of the ARM instruction set but encoding these in a 16-bit or 2-byte pattern (or occasionally, a pair of such opcodes).
ARM7TDMI-S supports both ARM and Thumb instruction sets, with a defined mechanism for switching between instruction sets at natural program boundaries. This instruction set architecture is called ARMv4T.
Newer ARM processors support enhanced and extended versions of one or both of these instruction sets in ARMv5, ARMv6, and ARMv7 architectures, or may support a new 32-bit instruction set for a 64-bit datapath architecture in ARMv8, either instead of or alongside ARM- and Thumb-compatible instruction sets.
D : Contains Debug extensions
The debug extensions provide the mechanism by which normal operation of the processor can be suspended for debug, including the input signal ports to trigger this behavior. For example, this could be a signal to allow a breakpoint to be indicated and a signal to allow an external debug request to be indicated.
M : Enhanced (relative to earlier ARM cores) 32x8 Multiplier block
Earlier ARM processors (before ARM7TDMI) used a smaller, simpler multiplier block that required more clock cycles to complete a multiplication. The introduction of this more complex 32x8 multiplier reduced the number of cycles required for a multiplication of two registers (32-bit * 32-bit) to a few cycles (data dependent). Modern ARM processors are generally capable of calculating at least a 32-bit product in a single cycle, although some of the smallest Cortex-M processors provide an implementation choice of a faster (single-cycle) or a smaller (32 cycle) 32-bit multiplier block.
I : EmbeddedICE macrocell
The EmbeddedICE macrocell consists of on-chip logic to support debug operations. In the ARM7TDMI-S processor, this includes two instruction breakpoint and data watchpoint comparators, an Abort status register, and a debug communications channel to pass data between the target and the host. The EmbeddedICE interacts with the debug extensions, for example to signal a halt to the processor when a breakpoint is met.
-S : synthesizable (that is, distributed as RTL rather than a hardened layout)
ARM7TDMI (without the "-S" extension) was initially designed as a hard macro, meaning that the physical design at the transistor layout level was done by ARM, and licensees took this fixed physical block and placed it into their chip designs. This was the prevalent design methodology at the time. Subsequently, demand increased for a more flexible and configurable solution, so ARM moved towards delivering processor designs as a behavioral description at the 'register transfer level' (RTL) written in a hardware description language (HDL), typically Verilog HDL. The process of converting this behavioral description into a physical network of logic gates is called 'synthesis', and several major EDA companies sell automated synthesis tools for this purpose. A processor design distributed to licensees as an RTL description (such as ARM7TDMI-S) is therefore described as 'synthesizable'.
Processor designs newer than the ARM9TDMI generally provide basic or upgraded versions of all the features represented by this suffix, but the suffix itself was dropped from the names so that these features are implied rather than explicit in the naming scheme. This allowed more distinctive features to be represented in the suffixes of ARM11 processor names without the name suffixes becoming too cumbersome.
E: Enhanced DSP instruction set support
Supports an extended set of DSP-related functions, such as saturating arithmetic and Single Instruction Multiple Data (SIMD) vector-style instructions, for example adding two 32-bit registers as four parallel 8-bit additions rather than a single 32-bit addition.
J : Java bytecode execution support
Native execution of some Java bytecodes without requiring translation into the ARM or Thumb instruction sets.
F : Hardware floating-point support
The processor includes an extended instruction set to process floating-point arithmetic.
T2 : Supports the Thumb-2 technology extension
Extends the original Thumb instruction set by adding more double-opcode instructions, to enable a complete system to be implemented using only Thumb instruction mode.
Z : TrustZone
Supports ARM TrustZone software security implemented in the processor hardware. This is based on separating memory and resources into Secure and Non-secure worlds, and providing a tightly controlled procedure for transitioning between the Non-secure and Secure security states.
Subsequent to the ARM11 family, this entire naming scheme was retired and replaced with the three profiles ( A - Application, R - Real-time and M - Microcontroller ) of the 'Cortex' processor family.