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How to determine if the Cortex-M3 or Cortex-M4 processor is in Thread or Handler mode

Article ID: 103488176

Published date: 13 Feb 2018

Last updated: -

Applies to: Cortex-M3, Cortex-M4


How can you tell if the Cortex-M3 or Cortex-M4 processor is in Thread or Handler mode?


Software or the debugger can inspect the Interrupt Program Status Register, IPSR.

If the ETM interface is enabled, logic on-chip can use the ETMINTNUM[8:0] output bus to observe the corresponding value. This interface is available irrespective of whether the ETM is licensed and whether the ETM is instantiated in the configuration. The ETM interface is active when the TRCENA bit[24] of the Debug Exception and Monitor Control Register, DEMCR, is set.

The processor also has an output signal bus, CURRPRI[7:0], which represents the current preempting priority of the processor. However, this does not distinguish between exception priority in Handler mode and boosted base priority in Thread mode.

At reset, the processor adopts Privileged Thread mode. The IPSR/ETMINTNUM is zero while the processor is in Thread mode (privileged or unprivileged), and changes to the corresponding exception number (that is, the vector table index) when an exception is being processed or handled.

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