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Does the Cortex-M3 or Cortex-M4 Embedded Trace Macrocell support Cycle-Accurate Trace?

Article ID: 103488381

Published date: 29 Nov 2017

Last updated: -

Applies to: Cortex-M3, Cortex-M4


Does the Cortex-M3 or Cortex-M4 Embedded Trace Macrocell support Cycle-Accurate Trace?



Cycle accurate trace is an optional feature of Embedded Trace Macrocell (ETM) architecture and is not included in the Cortex-M3 processor implementation.

Cycle accurate trace is not included in Cortex-M3 for the following reasons:

  • For optimal cost, the Cortex-M3 processor is targeted at minimal gatecount and pincount.

  • The Cortex-M3 processor has a simple pipeline and no out-of-order execution of opcodes.

Cycle accurate trace is considered to be of less value for the Cortex-M3 processor compared to more complex processors that contain more complex pipelines and instruction execution order.

For similar reasons, data tracing is also not supported in the Cortex-M3 ETM. However, reduced data trace functionality can be provided through the Data Watchpoint and Trace (DWT) and Instrumentation Trace Macrocell (ITM) units. The DWT contains up to four comparators, which can each trace data accesses to an address or range of up to 32KB addresses. The ITM can trace interesting values through explicit store instructions in the program code. For example, storing an interesting variable or register value to one of up to 32 ITM channels.

To identify the ETM features that are either support or not can be done by comparing the following with each other:

  • The full features of ETM Control Register, ETMCR, in the ARM Embedded Trace Macrocell Architecture Specification.

  • The implementation defined ETMCR bits that are either available or tied off in the ETM chapter in the Arm Cortex-M3 Technical Reference Manual.


The Cortex-M4 ETM functionality is identical to the Cortex-M3 ETM with respect to cycle accurate tracing and data tracing.

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