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Purpose of the DWT Function Registers 0-3. They each contain a different set of fields.

Article ID: 103488836

Published date: 24 Jul 2017

Last updated: -

Applies to: Cortex-M3, Cortex-M4


What do the DWT Function Registers 0-3 do? They each contain a different set of fields.


There are areas of functionality that do not occur symmetrically across all of the comparators, and this is why there are irregular results between registers 0 to 3. Specifically:

  • Comparator #0 has the ability to compare against a free-running cycle counter based on the CYCMATCH bit[7].

  • Comparator #1 has the ability to provide a data value matching function associated with up to two other comparators that are performing address matching. This function is enabled by the DATAVMATCH bit[8], but also involves several other fields DATAVADDR1, DATAVADDR0, DATAVSIZE and LNK1ENA, which are therefore only populated in the function register for comparator #1. Because the DATAVADDRx fields point to other comparators, and because the Cortex-M3 processor's DWT supports only four comparators, these fields need be populated only in two of the four possible bit positions.

It is important to note that the presence of 'reserved' fields in the function registers means that you must be careful to modify the function register contents using a 'read-modify-write' procedure, to avoid changing the 'reserved' fields. Although the reserved fields are generally not implemented in the current hardware, they might in future be defined to control additional features (as indeed the data matching function fields were previously undefined). Therefore any code that writes fixed values to these fields might cause unwanted side-effects if reused in future on a version where additional functionality is controlled by bits in those positions.

All except one of the function register bits is reset to '0'. The bit that resets to '1' is the LNK1ENA in comparator #1, which says that if you are using comparator #1 to provide data value matching in conjunction with address matching in other comparators (that is, if you set bit[8] to enable data value matching), then you are linking the data matching to the comparator specified in both DATAVADDR1 and DATAVADDR0. In other words, LNK1ENA means you want data value matching in two addresses or address ranges rather than just in one address or address range. Because DATAVMATCH is reset to '0' then the reset value of LNK1ENA is really irrelevant.

For interest, the results after writing 0xFFFFFFFF to each function register show all of the writable bits in each register set to '1'. Note that this will result in undefined behavior, but the resulting function register values are as follows:

All function registers include 0x2F, which means an undefined functionality of FUNCTION=0b1111 and enabling outputting of the range offset EMITRANGE=0b1 when an address match is made in an address range (where the least significant address bits are masked).

Comparator #0 has the CYCMATCH=1 function enabled, that is it will compare against the cycle counter rather than the data address.

Comparator #1 has data value matching (DATAVMATCH=1) linked to two other comparators for address matching (LNK1ENA=1) where the size of the data field being matched is Undefined (DATAVSIZE=0b11). For data value matching, comparator #1 is using address comparisons from comparator #3 (DATAVADDR0=0b11) and comparator #3 (DATAVADDR1=0b11). Again this is not a useful setting because the same comparison is being run twice.

MATCHED bit[24] is a status bit, which is cleared on a read. As you would expect, it is not directly writable.

The DWT is intended to generate debug events, ETM triggers, or trace packets when a data access by the processor meets the specified conditions, or in the special case for comparator #0 of when a particular cycle count is reached. Also, there are two function codes for each comparator allowing the comparator to compare against the PC value itself; one to generate ETM trigger events, and one to generate watchpoints (debug events). ARM does not recommend the latter because the FPB unit performs the same function but does it better - the FPB unit can be used to give a proper breakpoint exactly at the time the instruction was about to be executed, but conversely the DWT will trigger after that instruction is executed. However, if you want to generate an ETM trigger event based on this opcode being executed then you could do this with the DWT comparator.

The 'PC Match' functions always use a 32-bit comparison. Therefore you do not need to set the DATAVSIZE (although you can still use the MASK to extend the range of PC values you are matching), and the LSB, PC[0], is considered to be '0' during this comparison so that your COMP value should be even.

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