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Cortex-M3 processor fetches from Peripheral and External Device memory

Article ID: 103488899

Published date: 24 Jul 2017

Last updated: -

Applies to: Cortex-M3, Cortex-M4


Why does the Cortex-M3 TRM imply that the Cortex-M3 processor can fetch from Peripheral and External Device memory?


Table 3-2 of the Cortex-M3 Technical Reference Manual (ARM DDI 0337) is correct because the MPU can override the default memory properties of these regions shown in Table 3-2. (There is also a semantic argument about whether a 'fetch' takes place to an 'XN' region in any case, because the 'XN' does not prevent the I-side read from the memory, but only prevents the eventual execution of the resulting opcode.)

Table 3-2 represents the attributes of the default memory map. The MMU can override most of these attributes, which is not stated explicitly, but can be inferred from the notes in the Private Peripheral Bus and System segments, which specify that the XN attribute on PPB and System space may NOT be overridden by the MPU.

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