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Avoiding spurious ECC errors in Cortex-M7 TCM

Article ID: 103489479

Published date: 10 Jan 2018

Last updated: -

Applies to: Cortex-M7


Avoiding spurious ECC errors in Cortex-M7 TCM


The Cortex-M7 processor can optionally be implemented with local private RAM, known as Tightly-Coupled Memory (TCM), occupying address ranges based at address 0x0 for Instruction TCM and at address 0x20000000 for Data TCM.

The TCMs can optionally be implemented with Error-Correcting Code (ECC) logic included. This methodology increases the word width of the memory blocks, so that a word contains both a data value (32- or 64-bits) and additional ECC bits. The ECC bit values are calculated when the memory word is written, and are verified when the word is read back.

The Cortex-M7 processor will make speculative reads to memory in a number of circumstances, and this behavior cannot be suppressed.

If the processor makes a speculative read to an uninitialized word in TCM, and ECC has been implemented in this chip, the ECC bits may not be correctly set for this word. In this case, in the system attempts to perform error correction. If the uninitialized data and ECC is perceived to represent a double bit error, this could trigger the system to initiate some system-dependent major fault handling sequence.


Programmers writing boot code for a Cortex-M7 must check the documentation of the chip that they are programming, in order to verify whether the chip contains TCM with ECC.

Where TCMs are implemented with ECC enabled in a chip, boot code should pre-initialize all uninitialized TCM addresses, for example by writing all zeros, to avoid spurious ECC fails on any speculative reads.





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