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Which pins of Cortex-M3 and Cortex-M4 can be excluded from toggle coverage?

Article ID: 103489490

Published date: 24 Jul 2017

Last updated: -

Applies to: Cortex-M3, Cortex-M4

Problem/Question

Which pins of Cortex-M3 and Cortex-M4 can be excluded from toggle coverage?

Scenario

This knowledge article is for verification engineers who are running test simulations on a Cortex-M3 or Cortex-M4 based SoC design.

Answer

The following tables contain information about the output pins on the Cortex-M3 and Cortex-M4 module boundary where it is expected not to see the pin values to change during simulation. Therefore these pins can be safely excluded from toggle coverage in verification.

I-Code interface

Signal

Bits

Comment

HADDRI

[31:29]

Only addresses between 0x00000000 - 0x1FFFFFFF accessed on this interface
HADDRI[31:29] : Always 3'b000

HADDRI

[1:0]

All accesses on this interface are WORD aligned
HADDRI[1:0] : Always 2'b00

HTRANSI

[0]

All accesses on this interface performed as
2'b00 = IDLE
2'b10 = NONSEQUENTIAL

HSIZEI

[2:0]

All accesses on this interface performed as
3'b010 = WORD

HBURSTI

[2:0]

All accesses on this interface performed as
3'b000 = SINGLE

HPROTI

[3:2]

HPROTI[2] : Always 0 = NONBUFFERABLE
HPROTI[3] : Always 1 = CACHEABLE

MEMATTRI

[1:0]

MEMATTRI[0] : Always 1 = ALLOCATE
MEMATTRI[1] : Always 0 = NONSHAREABLE

D-Code interface

Signal

Bits

Comment

HADDRD

[31:29]

Only addresses between 0x00000000 - 0x1FFFFFFF accessed on this interface
HADDRD[31:29] : Always 3'b000

HSIZED

[2]

All accesses on this interface performed as
3'b000 = BYTE
3'b001 = HALFWORD
3'b010 = WORD

HBURSTD

[2:1]

All accesses on this interface performed as
3'b000 = SINGLE
3'b001 = INCR

HPROTD

[3:2],[0]

HPROTD[0] : Always 1 = DATA ACCESS
HPROTD[2] : Always 0 = NONBUFFERABLE
HPROTD[3] : Always 1 = CACHEABLE

MEMATTRD

[1:0]

MEMATTRD[0] : Always 1 = ALLOCATE
MEMATTRD[1] : Always 0 = NONSHAREABLE

System interface

Signal

Bits

Comment

HSIZES

[2]

All accesses on this interface performed as
3'b000 = BYTE
3'b001 = HALFWORD
3'b010 = WORD

HBURSTS

[2:1]

All accesses on this interface performed as
3'b000 = SINGLE
3'b001 = INCR

HTM interface

Signal

Bits

Comment

HTMDHSIZE

[2]

Accesses can be
3'b000 = BYTE
3'b001 = HALFWORD
3'b010 = WORD

Workaround

No workaround.

Example

No example.

Related Information

None.

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