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What are the functions of the CLKCHANGE and TSCLKCHANGE ports

Article ID: 103489502

Published date: 13 Feb 2018

Last updated: -

Applies to: CoreSight Debug and Trace




The Knowledge Article is for chip designers who are designing a CoreSight-compatible trace system using a global timestamping capability.

CoreSight trace sources which support global timestamping may provide an input signal port with a name such as CLKCHANGE or TSCLKCHANGE. These ports allow on-chip logic to inform the trace source when there is a change to the trace clocking.


Some versions of documentation refer to a requirement to pulse this input signal HIGH only when the ratio between the ETM clock frequency and the timestamp counter clock frequency changes.

However, the correct requirement intended in the CoreSight architecture is for the clock change signal to be pulsed HIGH when either the ETM (or other trace source) clock frequency or the timestamp counter clock frequency changes. This means that a pulse should be supplied, even if the change in frequency does not cause a change in ratio.

The purpose of this signal is to inform the trace tools that any previously inferred frequency relationships may have changed, and should therefore be recalculated for future reference. Because this takes some time to complete, it does not matter if the pulse timing varies by a few cycles from the actual change of clock frequency.





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