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What is the maximum frequency of debug and trace clocks in a CoreSight design?

Article ID: 103489519

Published date: 01 Dec 2017

Last updated: -

Applies to: CoreSight Debug and Trace

Question

What is the maximum frequency of debug and trace clocks in a CoreSight design?

Answer

The ARM IP and protocol specifications do not specify any requirement on the JTAG or SWD clock speed or trace output frequency. These clock domains are entirely asynchronous to the processor clock speed.

They are limited by:

  • the signal integrity characteristics of your:

    • I/O buffers

    • wires

    • connection header

    • board traces

    • package balls

    • bond wires

  • the limitations of your:

    • debug run control unit

    • trace port analyzer

For example, ARM's DSTREAM can support a debug clock frequency of up to 60MHz and a trace data rate of up to 600Mb/s (TRACECLKIN 600 MHz, TRACECLK = 300MHz)

For information on DSTREAM, see http://ds.arm.com/ds-5/debug/dstream/.

Related information

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