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Can the Cortex-M3 or Cortex-M4 processor make a simultaneous instruction fetch and data access to code space?

Article ID: 103489807

Published date: 28 Feb 2018

Last updated: -

Applies to: Cortex-M3, Cortex-M4

Problem/Question

Can the Cortex-M3 or Cortex-M4 processor make a simultaneous instruction fetch and data access to code space?

Scenario

Code space is defined in the Armv7-M Architecture as the address range from 0x0 to 0x1FFF_FFFF.

In Cortex-M3 and Cortex-M4 processors, the code space is accessed through physically separate interfaces, instruction code and data code, while addresses above 0x2000_0000 are accessed through the System interface and PPB interface.

Answer

You must configure this processor feature in hardware during the chip design.

The configuration decision is based upon what kind of interconnect is placed between the processor code space bus interfaces and the memories that they can access.

The processor is supplied to you with example bus multiplexers that can be used for the code space.

The code mux is a simple combinatorial multiplexer which requires that the processor does not issue simultaneous accesses. You can ensure this by tying the configuration signal DNOTITRANS to 0b1.

The flash mux is a more sophisticated bus multiplexer which can arbitrate between simultaneous accesses, and therefore, works most efficiently with DNOTITRANS tied to 0b0.

Chip designers using the Cortex-M4 Integration Kit as an example design should note that comments in some versions of the Cortex-M4 Integration Kit suggest that the flash mux requires DNOTITRANS to be 1'b1. This is not correct. The default value for DNOTITRANS in the Integration kit is controlled by define ARM_CODEMUX, and the default value is 0b1, but this can safely be changed to 0b0 by commenting out that define when using the flash mux or any other sophisticated bus matrix component capable of handling simultaneous requests.

Workaround

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Example

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Related Information

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