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What AHB-Lite burst lengths do the Cortex-M3 and Cortex-M4 processors produce?

Article ID: 103489830

Published date: 28 Feb 2018

Last updated: -

Applies to: Cortex-M3, Cortex-M4

Question

What AHB-Lite burst lengths do the Cortex-M3 and Cortex-M4 processors produce?

Answer

Cortex-M3 and Cortex-M4 processors use AHB-Lite INCR bursts (incrementing address, unspecified number of transfers) for all data transfers (loads and stores). For single load and store operations, the transfer is always marked as NONSEQ (non-sequential), meaning that each burst has a length of one transfer, and is Byte, Halfword or, Word size, depending on data size qualifier on the instruction used.

Instruction fetches use SINGLE transfers. Fixed-length burst types are not used at all.

Instructions that transfer multiple Arm registers (LDM, STM, PUSH, and POP) always have a size of Word, and the burst length is equal to the number of registers in the register list transferred. This could be up to all 16 Arm registers R0-R15 in the programmer's register bank. However, the instruction encodings for these instructions available in the Armv7-M instruction set allow only a maximum of 14 registers to be transferred in any one instruction.

INCR bursts are also used for stacking operations during exception entry and exit. These sequences consist of a burst of two words for PC and xPSR followed by a burst of six words for R0-R3, R12, and LR. For a Cortex-M4 processor that includes a Floating-point Unit (FPU), exception stacking might add a burst of 17 words for floating-point registers S0-S15 and FPSCR. In some cases, where a register in S0-S7 is pending an update at exception entry, the floating-point registers might be stacked using three bursts of 8, 8 and 1 transfers respectively.

Because exception entry and exit with the extended floating-point stack frame automatically manages S0-S15 in accordance with the Procedure Call Standard for the Arm Architecture (AAPCS), any additional requirement for managing floating-point registers at exception entry and exit is likely to require pushing and popping of only up to 16 single precision 32-bit registers S16-S31. However, it is possible to write code which uses VLDM or VSTM to transfer any number of consecutive floating point registers up to all 32 single precision 32-bit registers, resulting in an INCR burst of 32 word transfers.

Therefore, the maximum burst length for Cortex-M3 or Cortex-M4 processor without the FPU configured and enabled, is 14.

The maximum burst length for the Cortex-M4 processor with the FPU enabled is 32, though in many cases does not exceed 17.

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