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How can ICSR show a pending interrupt PENDSTSET but no VECTPENDING?

Article ID: 103489912

Published date: 31 Jan 2018

Last updated: -

Applies to: Cortex-M3, Cortex-M4


How can ICSR show a pending interrupt PENDSTSET but no VECTPENDING?


Reading the Interrupt Control and State Register (ICSR) shows the instantaneous state of some internal processor signals relating to interrupt handling. When an interrupt becomes pending, its pending status bit becomes set. However, it takes a further clock cycle for the prioritization logic tree to determine whether a pending interrupt (and which of multiple pending interrupts) will pre-empt the current execution stream.

Therefore when the ICSR is read at the same time as a SysTick interrupt is triggered, the value returned depends upon the exact cycle in which the register is read relative to the cycle in which the interrupt is pended. For example, the returned value could be 0x04000000 in the cycle where SysTick becomes pended, or 0x0400f000 in the following cycle where the priority has been arbitrated and the SysTick is indicated as the VECTPENDING.

VECTPENDING is not intended for application code use cases; the design intent is to provide an indication during debug about what the processor expects to do next.

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