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How to implement a re-entrant interrupt within the Cortex-M exception model

Article ID: 103489917

Published date: 24 Jul 2017

Last updated: -

Applies to: Cortex-M3, Cortex-M4


How can I implement a re-entrant interrupt within the Cortex-M exception model?


The Cortex-M exception model precludes re-entrant interrupts because an interrupt at a given priority level cannot pre-empt an interrupt at the same pre-empting priority level, and if the priority of an interrupt is raised while the handler is active, the current active priority is also raised accordingly. Therefore a given interrupt can never have enough priority to pre-empt its own handler.


'The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors' (ISBN 978-0-12-408082-9) includes an illustration of how to create a synthetic re-entrant interrupt. See Section 23.6 on page 750 of the Third edition of the book.

The method basically depends upon creating a fake exception stack frame so that the processor can return to Thread mode to execute the body of the handler, which itself ends with an SVC call to restore the original exception stack frame. In this way, a new occurrence of the interrupt can interrupt the body of the handler.

This method requires the interrupt in question to be at the lowest available pre-empting priority in the system, because the return to thread mode from the fake stack frame would be a fault if any other exception handler were still active at that time. The user must take care about stack overflow, because re-entrant interrupts could cause significant and theoretically unlimited increase in stack size.


No workaround.


No example.

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