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How do Cortex-M3 and Cortex-M4 conform to the ARMv7-M Architecture for Load and Store Exclusives?

Article ID: 103489935

Published date: 21 Feb 2018

Last updated: -

Applies to: Cortex-M3, Cortex-M4

Question

How do Cortex-M3 and Cortex-M4 conform to the ARMv7-M Architecture for Load and Store Exclusives?

Answer

The architecture defines several alternate possibilities and IMPLEMENTATION DEFINED cases. A realistic understanding of the processor behavior might be easier to understand than the full architectural description.

The processor provides a very minimal implementation of Exclusives to minimize gatecount.

It ignores the Shareability attribute of the memory region.

The local monitor's Exclusives Reservation Granule is 4GB, indicating that no address information is stored in the local monitor.

Any LDREX instruction issues a bus access marked with EXREQx = 0b1. This leaves the local monitor in Exclusive state. If the memory system includes a global exclusive monitor covering this address, the monitor should record a tag for this address from this bus master.

A STREX only appears on the bus if the local monitor is already in the Exclusive state. The STREX is marked with EXREQx = 0b1 and the processor is sensitive to EXRESPx (as the status value returned in Rd) irrespective of shareability.

Therefore, the memory system must return the correct value of EXRESPx for any STREX. These values are:

  • 0 - For any memory address which cannot be written by any other agent in the system (exclusivity guaranteed by design). This means that either the hardware design does not permit access from another agent, or that there is a way of ensuring that software does not attempt an exclusive operation at a time when another agent (for example, a DMA engine) is active in this address region.

  • (x!=t) for any memory which is managed by an external exclusive monitor (exclusive success [EXRESPx=0] if the address 'x' matches the valid current tag 't' for this master, otherwise exclusive fail [EXRESPx = 1] if the address and tag do not match)

  • 1 for any memory address which is not managed by an external exclusive monitor but can be modified by another agent in the system (exclusivity cannot be determined or depended upon). Marking a memory to always reject exclusive transfers prevents semaphore operations from ever completing successfully in this address range.

Note:

A Real-Time Operating System (RTOS) is likely to make use of exclusive operators to implement semaphores. For a design containing multiple processors, it is preferable that all memory is guarded by a global exclusive monitor. For a design containing a single processor and some other agent such as a DMA controller, it is acceptable to tie EXRESPx = 0 if software which makes use of semaphore operations can ensure that the other agent is not accessing that address range while the semaphore operation is in progress.

EXREQx is an additional ("sideband") signal timed in the address phase of the AHB-Lite protocol. EXRESPx is a sideband signal timed in the corresponding data phase of AHB-Lite. This behavior might appear on the System Bus (EXREQS, EXRESPS) or D-Code Bus (EXREQD, EXRESPD).

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