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What is the ID Code of a Cortex-M0 DAP or Cortex-M0+ DAP?

Article ID: 103489943

Published date: 13 Feb 2018

Last updated: -

Applies to: Cortex-M0, Cortex-M0Plus, CoreSight Debug and Trace


What is the ID Code of a Cortex-M0 DAP or Cortex-M0+ DAP?


A CoreSight-compatible Debug Access Port (DAP) contains a Debug Port Identification Register (DPIDR) to allow a debugger to recognize which Debug Port (DP) component is present. The fields within the DPIDR are described the ARM Debug Interface v5 Architecture Specification (ADIv5).

The CM0DAP (r0p0) has an ID code of 0x0BB11477, regardless of which debug protocol you use - JTAG or Serial Wire Debug (SWD). This value shows a part number (PARTNO) of 0xBB, which is distinct from the standard CoreSight JTAG-DP and SW-DP part number of 0xBA. PARTNO 0xBB indicates that this DP is designed by ARM, conforms to architecture version 1 and uses the Minimal Debug Port (MinDP) implementation.

  JTAG_DPIDR_REG_VAL  = 32'h0BB11477;
SW_DPIDR_REG_VAL = 32'h0BB11477;

The Cortex-M0+ r0p0 customized DAP (CM0PDAP) conforms to DP architecture version 1 described in the ADIv5.1 Supplement and later versions. However, if the Multi-Drop Serial Wire option is implemented (an RTL configuration option), the DP conforms to DP architecture version 2. The PARTNO of this MinDP is 0xBC and the VERSION field reflects the DP architecture version, giving DPIDR identities as follows:

  JTAG_DPIDR_REG_VAL  = 32'h0BC11477;
SW_DPIDR_REG_VAL1 = 32'h0BC11477; // DP Architecture 1
SW_DPIDR_REG_VAL2 = 32'h0BC12477; // DP Architecture 2

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