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Does the Cortex-M3 or Cortex-M4 processor need Memory Barrier instructions?

Article ID: 103490176

Published date: 28 Feb 2018

Last updated: -

Applies to: Cortex-M3, Cortex-M4

Question

Does the Cortex-M3 or Cortex-M4 processor need Memory Barrier instructions?

Answer

For early versions of Cortex-M3, it is recommended to insert a Data Synchronization Barrier (DSB) before any Wait For Interrupt (WFI) to ensure that Erratum 548721 can not cause a problem. If you know that the processor is Cortex-M3 r2p0 or newer, or a Cortex-M4, this is not necessary as the erratum is corrected in r2p0.

In general, the Cortex-M3 or Cortex-M4 processor does not require memory barrier instructions for simple memory accesses because all memory accesses are executed in-order.

Memory accesses which have side-effects such as altering the memory system (for example, memory map changes) should be used with memory barriers to ensure that the change is complete before further memory accesses are initiated.

It is good practice to consider adding memory barrier instructions for any code which makes multiple memory accesses and relies on the processor correctly ordering the transfers. Cortex-M3 and Cortex-M4 processors perform memory accesses in program order, but more complex cores might permit out-of-order completion. Therefore, including memory barriers makes code more portable.

It is not necessary to insert memory barriers for Read-After-Write or Write-After-Read to the same address, because the processor cores include hazard checking for these cases. If external levels of buffering are included in the SoC, then the designer must take care of these hazards in the external buffering logic.

A detailed explanation of all the cases in which a Barrier might be required is included in the following application note:

https://developer.arm.com/products/architecture/m-profile/docs/dai0321/latest/application-note-321-arm-cortex-m-programming-guide-to-memory-barrier-instructions

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