How to enter Debug Halt state on a Cortex-M processor?
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How to enter Debug Halt state on a Cortex-M?
The C_DEBUGEN bit of the Debug Halting Control and Status Register (DHCSR) can only be programmed via the DAP, so you cannot halt the core without a debugger. Therefore, you will need to have some sort of debug simulation model to halt the core.
Once the C_DEBUGEN bit has been set, the core can be halted by setting the C_HALT bit of the DHCSR. This bit can either be written by the debugger or by software running on the core.