Late-arriving interrupt behavior
Article ID: 103490213
Published date: 13 Feb 2018
Last updated: -
Applies to: Cortex-M
What is the late-arriving interrupt behavior?
A late-arriving interrupt is an interrupt that is recognized after the processor has started its exception entry procedure.
If the late-arriving interrupt has higher pre-empting priority than the exception that the processor has already started to handle, then the existing stack push will continue but the vector fetch will be re-started using the vector address for the late-arriving interrupt. This guarantees that the interrupt with the highest pre-empting priority will be serviced first. However, in some circumstances, this results in some wasted cycles from the original vector fetch that was abandoned.
If the late-arriving interrupt has only equal priority to (or lower priority than) the exception that the processor has already started to handle, then the late-arriving interrupt will remain pending until after the exception handler for the current exception has run. This is because the late-arriving behavior is classed as a pre-empting behavior, and therefore depends only upon the pre-empting priority levels of the interrupts and exceptions.
Because the stack push has already been initiated, the interrupt latency (meaning the number of cycles between the arrival of the interrupt request and execution of the first instruction of its handler) might be less than the standard interrupt latency for the particular processor and system. Some (but not all) Cortex-M processors provide an implementation-time option for the chip designer to specify a minimum value for the interrupt latency, reducing or removing the uncertainty in interrupt latency by adding stall cycles in such cases. Documentation of the specific chip should provide details of this setting, if applicable.