The JTAG IDCODE for a Cortex processor
Information in this article applies to:
- CoreSight Debug and Trace
What is the correct JTAG IDCODE for my Cortex processor?
The Cortex families of processors are designed to comply with the Arm CoreSight debug infrastructure, and therefore do not contain individual TAPs. Instead, they have a debug connection, which complies with the CoreSight Debug Access Port (DAP) requirements. A DAP consists of:
A Debug Port (DP) for external pin protocol (typically full JTAG or reduced pincount Serial Wire Debug).
One or more Access Ports (AP) communicating with debuggable components on buses inside the SoC.
A DAP bus linking the DP to one or more APs.
The Serial Wire or JTAG-Debug Port (SWJ-DP), or the simpler JTAG-only JTAG-DP, is a single JTAG-capable TAP controlling one or several debug subsystems in the SoC. If an SoC provides a JTAG debug interface and contains any CoreSight debug components, including any Cortex processor, you should expect to see the standard JTAG IDCODE of a single CoreSight SWJ-DP or JTAG-DP as one TAP on the JTAG chain.
The CoreSight protocol indicates that when a debugger identifies the debug connection as a CoreSight DP, it should then interrogate the DAP bus to identify which Access Ports are present, for example, the Cortex-M processor's AHB Access Port - AHB-AP, or a general Debug APB Access Port - APB-AP. Any of the 256 possible slave ports on the DAP bus that is not occupied will read as zero. The debugger should interrogate the APs in each occupied slot on the DAP bus to find the ROM table for that AP, if it has one. This interrogation will to identify that debug subsystem's unique Peripheral ID code. It will then possibly continue, to identify the individual components that are contained in that sub-system, for example the Cortex core itself.
The IDCODE tells the debugger that it has connected to a revision of an SWJ-DP or JTAG-DP CoreSight Debug Port component, nothing more. You cannot infer anything about what CoreSight debug infrastructure is behind this DP simply from the IDCODE.
Individual IDCODE values should be included in the documentation for individual DP implementations.
Some example values for IDCODE in the DP delivered with various Arm IP products are included in the following table. There is no requirement that a Cortex processor is implemented together with any specific version of DP. Identifying the TAP as any version of CoreSight DP should trigger the debugger to commence the target identification procedure. This procedure consists of reading the associated Debug ROM Tables, attempting to match the unique combination of Peripheral IDs with any known device and, if no match is found, interrogating each component referenced in any of the Debug ROM Tables.
|Product family||Debug Port||Revision||IDCODE|
|SoC-600||JTAG-DP (4-bit IR)||r0p0||0x0BA06477|
|JTAG-DP (8-bit IR)||r0p0||0x0BA07477|
|JTAG-DP (4-bit IR)||r0p1||0x1BA06477|
|JTAG-DP (8-bit IR)||r0p1||0x1BA07477|
|JTAG-DP (4-bit IR)||r0p2||0x2BA06477|
|JTAG-DP (8-bit IR)||r0p2||0x2BA07477|
|SoC-400||cxdapswjdp (4-bit IR)||r3p2||32'h6BA00477|
|cxdapswjdp (8-bit IR)||"||32'h0BA03477|
Clarification of PARTNO values