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The JTAG IDCODE for a Cortex processor

Article ID: 103490233

Published date: 13 Feb 2018

Last updated: -

Applies to: Cortex-A, Cortex-M, Cortex-R

Question

What is the correct JTAG IDCODE for my Cortex processor?

Answer

The Cortex families of processors are designed to comply with Arm's CoreSight debug infrastructure, and therefore do not contain individual TAPs. Instead, they have a debug connection, which complies with the CoreSight Debug Access Port (DAP) requirements. A DAP consists of:

  • A Debug Port (DP) for external pin protocol (typically full JTAG or reduced pincount Serial Wire Debug).

  • One or more Access Ports (AP) communicating with debuggable components on buses inside the SoC.

  • A DAP bus linking the DP to its one or more APs.

The SWJ-DP (or the simpler JTAG-only JTAG-DP) is a single JTAG-capable TAP controlling one or several debug sub-systems in the SoC. If an SoC provides a JTAG debug interface and contains any CoreSight debug components (including any Cortex processor) you should expect to see the standard JTAG IDCODE of a single CoreSight SWJ-DP or JTAG-DP as one TAP on the JTAG chain.

The CoreSight protocol indicates that when a debugger identifies the debug connection as a CoreSight DP, it should then interrogate the DAP bus to identify which Access Ports (such as the Cortex-M processor's AHB Access Port - AHB-AP, or a general Debug APB Access Port - APB-AP) are present. Any of the 256 possible slave ports on the DAP bus that is not occupied will read as zero. The debugger should interrogate the APs in each occupied slot on the DAP bus to find the ROM table for that AP (if it has one), so as to identify that debug sub-system's unique Peripheral ID code. It will then possibly continue, to identify the individual components contained in that sub-system, such as the Cortex core itself.

The IDCODE tells the debugger that it has connected to a particular revision of an SWJ-DP or JTAG-DP CoreSight Debug Port component, nothing more. You cannot infer anything about what CoreSight debug infrastructure is behind this DP simply from the IDCODE.

There is no requirement that a particular Cortex processor is implemented together with any specific version of DP. Identifying the TAP as a CoreSight DP should trigger the debugger to commence the target identification procedure of reading the Debug ROM Table, attempting to match the unique combination of Peripheral IDs with any known device, and if no match is found, interrogating each component referenced in any of the Debug ROM Tables.

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