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Clarification of the PARTNO value in the IDCODE of the CoreSight DAP Debug Port

Article ID: 103490404

Published date: 24 Jul 2017

Last updated: -

Applies to: CoreSight Debug and Trace

Problem/Question

I am confused about the PARTNO value in the IDCODE of my CoreSight DAP's Debug Port

Scenario

The ARM Debug Interface v5 Architecture Specification (ADIv5) revision 'A' contains:

[27:12] PARTNO Part Number for the DP. This value is provided by the designer of the Debug Port and must not be changed. Current DPs designed by ARM Limited have the following PARTNO values:

  • JTAG-DP 0xBA00

  • SW-DP 0xBA10

The CoreSight Components Technical Reference Manual (TRM) revision 'H' contains:

[27:12] PARTNO Part Number for the debug port. This value is provided by the designer of the Debug Port and must not be changed. Current ARM-designed debug ports have the following PARTNO values:

  • JTAG-DP 0xBA00

  • SW-DP 0xBA02

The SW-DP part numbers are inconsistent.

Answer

Read the supplementary document ADIv5.1 'ARM® Debug Interface v5 Architecture Specification ADIv5.1 Supplement' in conjunction with the ADIv5. This is document number DSA09-PRDC-008772.The ADIv5.1 document contains:

  • Errata for the ADIv5 document.

  • Extensions to the ADIv5 Architecture.

The code 0xBA10 for the SW-DP IDCODE PARTNO is a typographical error in the ADIv5, as noted in the errata section of ADIv5.1.

The ADIv5.1 introduces the concept of Multi-drop Serial Wire, where a single Serial Wire Debug (SWD) port can identify and control multiple SW-DPs over a single Serial Wire connection.

The ADIv5.1 refines the definition of the IDCODE bitfields within the range [27:12].

For JTAG-DPs, the PARTNO field remains IDCODE[27:12] = 0xBA00 for all current JTAG-DPs.

For SW-DPs, the corresponding bitfield is now divided into:

  • IDCODE[27:20] = PARTNO = 0xBA

  • IDCODE[19:17] = unknown

  • IDCODE[18] = M (Minimal) = 0 for regular DPs, 1 for reduced functionality DPs

  • IDCODE[15:12] = VERSION

The VERSION field currently takes one of the following values:

  • 0x1 : version 1 SW-DP, supporting a single SW-DP per SWD port.

  • 0x2 : version 2 SW-DP, supporting Muti-drop.

Registered users can download a zip file that contains both documents (as PDFs) from the ARM Silver service (https://silver.arm.com) under:Documentation ->

CoreSight on-chip trace & debug ->

Architecture Specifications ->

ARM Debug Interface v5 ->

PDF version

Note - the ADI versions discussed above are now (2017) superseded by ADIv5.2

Workaround

No workaround.

Example

No example.

Related Information

None.

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