Placement of APB system peripherals in the External Private Peripheral Bus (External PPB) space
Article ID: 103490439
Published date: 24 Jul 2017
Last updated: -
Applies to: Cortex-M3, Cortex-M4
Can I place APB system peripherals in the External Private Peripheral Bus (External PPB) space?
The External PPB (EPPB) space (0xE0040000-0xE0100000) is intended for CoreSight-compatible debug and trace components. It has some limitations that reduce its usefulness for regular system peripherals. ARM recommends that you place system peripherals in suitable (Device type) areas of the System bus address space, using an AHB2APB bridge (protocol converter) for APB-based devices.
Limitations of the EPPB space are:
It is accessible in privileged mode only.
It is accessed in little-endian fashion irrespective of the processor's data endianness setting.
Accesses behave as Strongly Ordered.
It does not make available a bit-band function.
Unaligned accesses have unpredictable results.
It supports only 32-bit data accesses.
It is accessible from the Debug Port and from the local processor, but not from any other agent (processor) in the system.
Use of regular System space and an AHB2APB bridge for system peripherals removes most of these restrictions and causes the peripheral accesses to behave as expected.