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Why do reads from Data Watchpoint Trace registers return unexpected values in Cortex-M3 and Cortex-M4?

Article ID: 103490461

Published date: 13 Feb 2018

Last updated: -

Applies to: Cortex-M3, Cortex-M4

Question

Why do reads from Data Watchpoint Trace (DWT) registers return unexpected values in Cortex-M3 and Cortex-M4?

Answer

The following DWT counter registers can only be accessed when the TRCENA bit in the Debug Exception and Monitor Control Register ( DEMCR) is set:

  • DWT_CYCCNT.

  • DWT_CPICNT.

  • DWT_EXCCNT.

  • DWT_SLEEPCNT.

  • DWT_LSUCNT.

  • DWT_FOLDCNT.

  • DWT_PCSR

The TRCENA bit must be set to 1 to enable use of the trace and debug blocks:

  • DWT.

  • Instrumentation Trace Macrocell (ITM).

  • Embedded Trace Macrocell (ETM).

  • Trace Port Interface Unit (TPIU).

If the TRCENA bit is not set, reads from the DWT counters return an unpredictable value, which might be related to the previous activity.

For example, if the DWT registers are read in order while TRCENA is clear, starting from DWT_CTRL, the counter register reads might return the value previously read from DWT_CTRL:

                        
# DEMCR = 00000000
#
# DWT_CTRL = 40000000
# DWT_CYCCNT = 40000000
# DWT_CPICNT = 40000000
# DWT_EXCCNT = 40000000
# DWT_SLEEPCNT = 40000000
# DWT_LSUCNT = 40000000
# DWT_FOLDCNT = 40000000
# DWT_PCSR = 40000000
#
# DEMCR = 01000000
#
# DWT_CTRL = 40000000
# DWT_CYCCNT = 0
# DWT_CPICNT = 0
# DWT_EXCCNT = 0
# DWT_SLEEPCNT = 0
# DWT_LSUCNT = 0
# DWT_FOLDCNT = 0
# DWT_PCSR = 57a

Related information

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