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How is a single core reset in a multi-core system?

Article ID: 123060232

Published date: 18 Oct 2017

Last updated: -

Applies to: Cortex-M23

Problem/Question

How is a single core reset in a multi-core system?

Scenario

In a single core system, the nHRESET signal can be asserted when there is an outstanding AHB transaction. This is because the nHRESET signal resets both the core and the AHB system. However, in a multi-core system, if only one core is reset, you might not want to reset the AHB system.

Answer

To ensure that a reset does not break the system, you must reset the processor that requires a reset. This is done after executing a WFI instruction and the processor has effectively entered sleep mode. The system also needs to ensure that the processor does not leave sleep mode during this time, for example, because of an interrupt. To ensure that the processor does not wake-up from sleep mode (request to extend sleeping) when an interrupt is asserted, use either the legacy SLEEPHOLDREQn or SLEEPHOLDACKn signals or the Q-Channel QREQn or QACCEPTn.

Workaround

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Example

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Related Information

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