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Enabling ITM trace on Serial Wire Viewer

Article ID: 128795835

Published date: 24 Jul 2017

Last updated: -

Applies to: Cortex-M3, Cortex-M4


I have enabled the ITM and sent data to the stimulus channels, but I am not seeing any trace on the Serial Wire Viewer output.


This knowledge article is relevant if you are trying manually to enable ITM or DWT trace on the single wire trace output Serial Wire Viewer pin of a Cortex-M3 or Cortex-M4 Trace Port Interface Unit, either in simulation or on a physical device.


There are several steps required for enabling the SWV trace.

Set DEMCR.TRCENA = 1 to enable access to the trace components' registers.

Select the required pin protocol in the TPIU_SPPR register:

0 - parallel synchronous trace port (not SWV)

1 - Serial Wire Viewer, Manchester encoding

2 - Serial Wire Viewer, UART Non-Return to Zero encoding

Write 0xC5ACCE55 to the ITM's CoreSight Lock Access Register (ITM_LAR) to unlock the ITM. This register is missing from some editions of the processor's Technical Reference Manual (TRM).

Set ITM_TCR.ITMENA = 1 to enable the ITM, together with additional bit fields in this register to enable timestamps, synchronization packets, and others as required.

Enable the individual channels as required by setting bits in ITM_TER0. You might also wish to control the privilege level of the stimulus channels by writing to the four least significant bits of ITM_TPR.

Write values to your enabled stimulus channels (ITM_STIM0 to ITM_STIM31) to generate SWV trace activity.





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