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Using DS-5 with Xilinx Zynq-7000 devices

Article ID: 137812646

Published date: 01 Nov 2017

Last updated: -

Applies to: DS-5 Development Studio

Problem/Question

What known issues relate to debugging/tracing some Xilinx Zynq-7000 based targets with DS-5?

Scenario

This article attempts to answer some of the questions that arise when end users consider using the DS-5 Debugger with Xilinx Zynq-7000-based evaluation boards.

Answer

DS-5 Professional and Ultimate editions provide debug and trace support for the Zynq-7000 based series of targets.

Connection is possible using DSTREAM or ULINKpro (D) devices.

Connecting the DSTREAM/ULINKpro  unit to Zynq-7000 targets

For the ZC702, connect the DSTREAM/ULINKpro  through the J58 connector (marked ‘JTAG’) as shown below :

images/ZC702.jpg

See also the Xilinx Answer Record here.

 

For the ZC706 board, connect the DSTREAM/ULINKpro through the J62 connector:

images/ZC706.jpg

 

If using a Zedboard, then the JTAG adaptor must be obtained, and the off-board connector labeled 'ARM DSTREAM' (circled in yellow below) is the one to connect the DSTREAM/ULINKpro to.

images/zedboard_JTAG.jpg

Configuring the DS-5 connection

There are two possible DS-5 JTAG configurations for the Zynq-7000 series of boards. These are known as 'Cascaded' and 'Independent' and are described below :

  • 'Cascaded' means that the Xilinx TAP is daisy-chained with the Arm DAP on the JTAG scan chain.

  • 'Independent' means that there is just the Arm DAP on the JTAG scan chain.

The 'Independent' setting can be used on the ZC702 and ZC706 boards but requires using a different connector and target configuration that must be performed by the user using the Xilinx tools.

Therefore, the one to use with the above boards and highlighted connectors is ‘Cascaded’.

Configure this from the 'Debug Configuration' window as shown :

images/Zynq7000_config_in_DS5_2.png

You should now be able to configure the connection and connect to the target.

Off-chip parallel Trace

Although off-chip parallel trace has been tested with DS-5 and DSTREAM using the ZC702 and ZC706 boards, the TPIU lines from the Xilinx SoC must be routed out to the appropriate expansion header.

Use the Xilinx-supplied Vivado tooling to perform this routing.

Also, an additional FMC XM105 debug card is required to implement the mictor-38 connector.

See also the Xilinx Answer record available here for the ZC702, and the Master answer record here.

High-Speed Serial Trace (HSSTP)

It is possible use Arm's HSSTP Probe with Xilinx development boards.

Although HSSTP uses the Aurora 8B/10B encoding specification, the CRC (Cyclic Redundancy Check) is calculated differently in the LogiCORE IP available from Xilinx when compared with that stated in the HSSTP Architecture Specification (available here).

The HSSTP specification uses a 4-byte CRC calculated per Aurora frame, whereas the LogiCORE IP calculates the CRC per lane.

Therefore, some work will be required by the end user to modify the LogiCORE so as to support the HSSTP standard.

 

Workaround

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Example

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Related Information

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