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What AHB5 transactions can the Cortex-M33 generate?

Article ID: 141718063

Published date: 18 Oct 2017

Last updated: -

Applies to: Cortex-M33

Problem/Question

What AHB5 transactions can the Cortex-M33 processor generate?

Scenario

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Answer

For the Cortex-M33 C-AHB and S-AHB interfaces the following combinations of AHB5 transactions are supported:

  • HTRANS: All types IDLE, NSEQ, SEQ, BUSY.

  • HNONSEC: All types when TrustZone included and enabled. Always 1’b1 if TrustZone not included. For debug requests, HNONSEC is dependent on processor level debug authorization and HNONSECD.

  • HSIZE: Byte, Halfword, Word supported. Bit[2] tied to 1’b0.

  • HBURST: Only INCR and SINGLE encodings used. Requests from software running on the processor (HMASTER=0) are always INCR. Requests from debug (HMASTER=1) are always SINGLE.

  • HPROT: All encodings supported by the ARMv8-PMSA supported (if the MPU is included).

  • HEXCL: 1’b1 for exclusive requests from memory addressed marked as shareable (or when ACTLR.EXTEXCLALL) is set. 1’b0 All other memory requests.

  • HMASTER: 1’b0 for accesses from software. 1’b1 for accesses from the debugger.

Debug requests to memory are initiated through the D-AHB interface. The following rules apply for how requests are reflected on the C-AHB/S-AHB interfaces:

  • HSIZED[2] is ignored – no transactions > 32-bits.

  • HBURSTD[2:0] is ignored – all debug transactions are singles.

  • HTRANSD[0] is ignored – all debug transactions are treated as Non-sequential (or Idle).

  • HPROTD[0] is ignored – all debug transactions are treated as Data accesses. All other HPROT bits are transferred directly from D-AHB to the processor master interfaces.

Workaround

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Example

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Related Information

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