You copied the Doc URL to your clipboard.

Using DS-5 with Xilinx UltraSCALE+ MPSoC devices

Article ID: 143055320

Published date: 01 Nov 2017

Last updated: -

Applies to: DS-5 Debugger


Known issues related to debugging/tracing Xilinx UltraSCALE+ MPSoC based targets with DS-5.


This article is intended to help the end user who intends to use the DS-5 Debugger with Xilinx UltraSCALE+ MPSoC devices.



DS-5 v5.27 (and later) Ultimate editions have support for the Xilinx UltraSCALE+ MPSoC device.

Connection is possible using DSTREAM or ULINKpro (D) devices.

Connectivity options are configurable for debug and trace of the 4x Cortex-A53 processors within the Application Processor Unit (APU) as well as the 2x Cortex-R5 processors within the Real-time Processing Unit (RPU) on this device.

Connecting the DSTREAM/ULINKpro to the target

When using the ZCU102, connect the DSTREAM/ULINKpro  unit to the Arm 20-pin JTAG connector J6, as shown below :



Attempting debugging of the target through P6, the mictor-38 connector labeled 'ARM Trace', will fail.


There is a mictor-38 connector fitted to this board (P6). However, out of the box, none of the trace data lines are routed to this connector. The Xilinx-supplied 'Vivado' tool must be used to configure this connector.

Once this connector is appropriately configured, off-chip trace capture is possible through P6. Off-chip trace has been tested by Arm, but the routing of the applicable trace data and trace clock lines to the mictor connector must be performed first.

See Xilinx Answer Record #66669 available here.

High-Speed Serial Trace (HSSTP) (all targets)

It is possible use Arm's HSSTP Probe with Xilinx development boards.

To configure the board for high-speed serial port trace, be sure to use the correct CRC.

Although HSSTP uses the Aurora 8B/10B encoding specification, the CRC (Cyclic Redundancy Check) is calculated differently in the LogiCORE IP available from Xilinx when compared with that stated in the HSSTP Architecture Specification (available here, registration required to access).

The HSSTP specification uses a 4-byte CRC calculated per Aurora frame, whereas the LogiCORE IP calculates the CRC per lane.

Therefore, some work will be required by the end user to modify the LogiCORE so as to support the HSSTP standard.





Related Information


Was this page helpful? Yes No