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VCD generation in Cortex-M33 processor Execution Testbench

Article ID: 183875318

Published date: 06 Jun 2018

Last updated: -

Applies to: Cortex-M33

Problem/Question

The method described in section 10.8.4 VCD generation in the Cortex-M33 Integration and Implementation Manual (IIM) does not work in some editions of the document.

Scenario

At the time of writing this article, the current released version of Cortex-M33 is r0p3.

This article is of interest to chip designers who have licensed the Cortex-M33 processor from Arm for inclusion in their chip design, and who want to debug simulations in the execution testbench environment.

The Cortex-M33 IIM is a confidential document provided to chip designers who have licensed the Cortex-M33 RTL description for inclusion of this processor in their chip design.

Chapter 10 Execution Testbench describes the execution testbench, execution_tb, which is an example MCU environment with a set of test programs that can be run in simulation to confirm the chosen configuration settings for the processor.

In some editions of the document, section 10.8.4 VCD generation of the document describes some settings in the netlist.vc file that can be used to generate a VCD waveform trace dump of the Cortex-M33 during simulation.

When simulating at the RTL level, these settings do not result in a VCD file being produced.

Answer

The netlist.vc file is used only for gate-level netlist simulations. The equivalent Verilog command file used for RTL simulations is rtl.vc. By default, this file does not contain the VCD settings.

The settings listed in the netlist.vc file can be copied into the rtl.vc file and the start and stop times adjusted to match your requirements.

However, recompiling the design in this way results in a compilation error, as the hierarchical instance for the VCD trace (specified in the tbench.v file), u_mcu.u_sys.u_tealmcu.u_TEAL.u_teal, does not exist in the RTL view. To successfully compile the design and generate VCD trace during the run, this instance specifier must be shortened by removing the final .u_teal from the hierarchical path.

Workaround

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Example

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Related Information

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