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What AXI IDs are used by Cortex-M7?

Article ID: 218345141

Published date: 05 Sep 2018

Last updated: -

Applies to: Cortex-M7

Problem/Question

What AXI IDs are used by Cortex-M7?

Scenario

This knowledge article refers to Cortex-M7 Processor Technical Reference Manual (TRM), version d, at the time of writing, June 2018.

Answer

A list of the AXI IDs for the five channels of the Cortex-M7's AXIM interface is presented in section 5.4.2 of the Cortex-M7 Processor Technical Reference Manual. The list covers all access types generated by the AXIM interface when the Cortex-M7 data cache is implemented and enabled.

If a Cortex-M7 is implemented without the data cache, or if the data cache is not enabled, then data accesses that would otherwise be handled by the cache are converted to Non-cacheable accesses, and use the Non-cacheable encodings. Therefore:

  • Normal cacheable data reads will use encoding 0b000.

  • Normal cacheable writes to Write-Allocate memory will use encoding 0b00.

Workaround

N/A

Example

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Related Information

None.

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