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Interrupt Priority and IRQLATENCY on Cortex-M33

Article ID: 224343334

Published date: 15 Aug 2018

Last updated: -

Applies to: Cortex-M33

Problem/Question

Interrupt Priority and IRQLATENCY on Cortex-M33

Scenario

This knowledge Article is relevant to chip designers who have licensed the Cortex-M33 RTL and who need to assign the processor interrupt input ports to different interrupt sources.

The Arm v8-M Architecture defines a priority scheme based on programming the NVIC_IPRn registers, but the Arm Cortex-M33 Processor Integration and Implementation Manual also describes an IRQLATENCY feature to specify which interrupts support the lowest interrupt latency. How are these two concepts related?

Answer

The Armv8-M architecture provides the priority scheme implemented in the NVIC_IPRn registers. This scheme determines which interrupts can preempt other interrupt handlers that are already running. Interrupts that are enabled and whose GROUP priority is programmed to be strictly higher (meaning a lower numerical value) than the current execution priority level, preempt the current execution. This is standard behavior across all Cortex-M processors.

Specifically, on older processors like Cortex-M3, the priority decision logic is a simple, single-cycle logic cone. If you select a large number of interrupts and a large number of priority levels implemented in hardware, then the priority decision can become the critical path, limiting the processor clock frequency.

In Cortex-M33, to avoid a very large single-cycle logic cone for prioritization that could become a critical path for timing closure, the priority decision is broken down into separate sections and the result of each section is compared to make the overall decision.

The interrupts that you select for IRQLATENCY are compared separately from the other interrupts. It is intended that you chose a small number of interrupts for this feature so that the logic cone is small. The remaining, non-IRQLATENCY interrupts are routed to a separate (possibly larger and slower) logic cone. The prioritization of the IRQLATENCY interrupts is completed one cycle earlier than the prioritization of the non-IRQLATENCY interrupts. This is the lowest interrupt latency that is referenced in the IIM.

So, in summary, you must try to specify IRQLATENCY for your most latency-sensitive interrutps, to save one cycle in making the prioritization decision. However, the processor always handles interrupts in the order of their programmed priority level even if the highest priority requested interrupt does not happen to be an IRQLATENCY interrupt and it therefore takes an extra cycle to get to the correct decision.

Chip designers who are making use of the TrustZone Arm v8-M security extension with Cortex-M33 might also be interested in the behavior of AIRCR.PRIS described here: https://developer.arm.com/docs/183875327/latest/aircrpris-behavior-in-cortex-m33

For licensees of older Cortex-M processors, please note that the IRQLATENCY feature on Cortex-M33 is entirely different from the feature with the same name on Cortex-M0+.

Workaround

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Example

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