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Is there a dependency between the two ACE master ports of the DSU?

Information in this article applies to:

  • Cortex-A55

  • Cortex-A75

  • Cortex-A76

Problem/Question

Is there a dependency between the two ACE master ports of the DSU?

Scenario

The DynamIQTM Shared Unit (DSU) can be configured as two AXI Coherency Extensions (ACE) master ports, m0 and m1. Is there a dependency between these two ports?

A partially issued transaction refers to transactions where either a request or data is issued to the interconnect, but not both. For example, the following cases are partially issued transactions:

  • AW is issued to the interconnect, but W is not.

  • CR is issued to the interconnect, but CD is not.

Does any partially issued transac tion of a port complete based only on the back-pressure on that port, or does the the partially issued transaction get blocked because of the back-pressure on another port?

Answer

In general, the two master ports are independent. However, if the interconnect puts back-pressure onto a channel that the DSU expects to be free-flowing, this back-pressure can cause stalls in the design. These stalls can prevent the other port from progressing.

The DSU ensures that, on a given port, partially issued transactions complete based on the back-pressure on that port. If the m0 port starts a transaction, this transaction completes based only on the back-pressure on the m0 port. This transaction is not blocked by the back-pressure on the m1 port.

Workaround

N/A

Example

N/A

Related Information

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