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Does an ECC error cause the CRRESP[1] bit to be asserted?

Information in this article applies to:

  • Cortex-A53

  • Cortex-A72

Problem/Question

In Cortex-A53 and Cortex-A72 processors, does a double-bit Error Checking and Correction (ECC) error in the L1 or L2 data RAMs cause the CRRESP[1] bit to be asserted?

Scenario

Imagine a multiple clusters system with either one Cortex-A53 cluster, or one Cortex-A72 cluster, or both clusters implemented. If a double-bit ECC error in the L1 or L2 data RAM is detected when an incoming snoop is received, does this error cause the CRRESP[1] bit to be asserted?

Answer

The answer depends on the type of snooped core:

  • If the Cortex-A53 cluster is snooped and there is a double-bit ECC error in the L1 or L2 cache data RAM of the processor, CRRESP[1] is asserted HIGH. Then nINTERRIRQ is asserted.

  • If the Cortex-A72 cluster is snooped and there is a double-bit ECC error in the L1 or L2 cache data RAM of the processor, CRRESP[1] is not asserted HIGH. The snooped Cortex-A72 cluster does not assert CRRESP[1] HIGH to inform the other cluster that initiates the snoop that there is an internal double-bit ECC error in its data RAM. However, the nINTERRIRQ signal of the Cortex-A72 cluster gets asserted and informs the system that there is a double-bit ECC error detected in the Cortex-A72 cluster.

Note: When a double-bit error occurs, the error cannot be corrected, and the system must be reset.

Workaround

N/A

Example

N/A

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