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Are there system design considerations for the DSU PACTIVEs synchronization?

Information in this article applies to:

  • DSU

Problem/Question

Are there system design considerations for the DSU PACTIVEs synchronization?

Scenario

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Answer

The DynamIQ™ Shared Unit (DSU) and the power controller are usually implemented with asynchronous clocks. As stated in the AMBA® Low Power Interface Specification (ARM IHI 0068C), Arm recommends that you implement separate synchronizers for each individual bit of PACTIVEs. Therefore, it is possible that a glitch can be observed on PACTIVEs when multiple bits of PACTIVEs toggle simultaneously.

The glitch on PACTIVEs might cause unwanted power mode transitions if the power controller sends the intermediate power mode request per the PACTIVE hints and the request is valid and is therefore accepted. Alternatively, if the intermediate power mode request is invalid, the intermediate power mode request is denied. However, the glitch must not cause any functional issue. This document covers the following system design considerations for the power controller to achieve this goal:

  • The power controller must not assume that the DSU always issues a power hint by PACTIVEs according to valid power mode transitions. The PACTIVEs indicate only the required minimum state.

Consider a normal cluster power-down sequence for example. The DSU issues the FULL_FUNC_RET hint before issuing the FULL_MEM_RET hint, although a transition from FULL_FUNC_RET to FULL_MEM_RET is not a valid power mode transition.

  • If a direct transition is not valid, the power controller must be aware of the valid transitions and request transitions through intermediate modes.

When an intermediate PACTIVE state is captured and the DSU accepts the power mode transition, the power controller must be able to send the power mode request for the target power mode, if the DSU allows the power mode transition from the intermedia power mode to the final target power mode.

If the power mode transition is not valid or not allowed, the power controller must be aware of the intermediate power mode of the DSU or cores. Then, the power controller sends a request or a series of requests to make the DSU or cores change to the target mode. For example, if the cluster is in FUNC_RET and CLUSTERPACTIVE indicates MEM_RET, then the power controller must first request a transition from FUNC_RET to ON. Only after this request has been completed, does the power controller request a transition from ON to MEM_RET.

Workaround

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Example

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