What happens to Cortex-M33 performance when the code and data are on the same bus?
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If I run code from the same bus where my data memory is located how does this affect performance?
Processors that have a Harvard architecture run most efficiently when the code and data are accessed through separate interfaces. This separation allows data loads and stores to occur without interrupting the fetching of instructions.
Official performance benchmark figures for Cortex-M33 are generated using this recommended arrangement, and with zero wait-state memory.
The Code AHB and System AHB interfaces on Cortex-M33 are symmetrical. If the code and data are accessed through the same interface, the Cortex-M33 system works correctly. However, there is a slight reduction in performance, due to contention between code fetches and data accesses.
The following results are from tests that were run on a prototype board with zero wait-state memory:
For Dhrystone MIPS, moving code and data from separate buses to the same bus results in the performance dropping from 1.481 DMIPS/MHz to 1.296 DMIPS/MHz.
For CoreMark, moving code and data from separate buses to the same bus results in the performance dropping from 3.8789 CM/MHz to 3.6765 CM/MHz.