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Information in this article applies to:

  • CoreSight Debug and Trace
  • Cortex-M


What is TSCLKCHANGE and which Arm IP supports it?


Most microprocessors that are designed by Arm provide implementation options to the chip designer, to allow streams of trace information to be exported from the processor. The trace streams comply with Arm's CoreSight on-chip debug and trace specifications. The trace streams are made up of trace packets that can be generated from components inside the processor, or from external components that are connected to the processor. The trace packets can be exported off chip through device pins and sent to a Trace Port Analyzer. The Trace Port Analyzer allows debug tools to present a visual representation of what the processor is doing.

The trace source for most Arm processors is an Embedded Trace Macrocell (ETM). An ETM can generate a trace stream that reports the instructions being executed in the processor. This is called Instruction Trace. An ETM might also be able to generate trace packets that record data load and store operations caused by instructions executing in the processor. This is called Data Trace.

Processors that conform to the Microcontroller profile of the Arm architecture might include separate trace sources. Data load and store operations might be traced by a Data Watchpoint and Trace unit (DWT). Specific data values of interest might also be traced by including instructions in the program code that send the interesting values directly to an Instrumentation Trace Macrocell (ITM). This form of program code is known as instrumented code, and this method of debugging is sometimes called printf-style debug.

The TSCLKCHANGE feature applies to some implementations of each of these trace mechanisms.


For each Arm processor that supports an ETM option, the ETM conforms to a specific version of Arm's CoreSight ETM architecture. The different versions of ETM architecture are covered by a small number of specification documents that each cover a range of ETM architecture versions. At the time of writing, the current specifications are:

  • Embedded Trace Macrocell™ ETMv1.0 to ETMv3.5 Architecture Specification

  • Arm® Embedded Trace Macrocell Architecture Specification ETMv4.0 to ETMv4.4

The ETMv3.5 architecture introduces the concept of timestamping of ETM trace packets. Timestamping allows the debug tools to correlate the exact times at which individual trace packets, perhaps from different sources within a system, were generated. In ETMv3.5, the timestamp packet header includes an 'R' bit that is used to indicate when the processor clock frequency or the timestamp generator clock frequency has changed. ETMv3.5 requires that a trace packet, with the 'R' bit set, is sent out when a frequency change occurs.

In a system that includes an ETMv3.5 ETM, the clock generation logic in the system must supply a signal pulse to indicate to the ETM when a clock frequency change has occurred. The input signal name on the ETM is typically TSCLKCHANGE.

It was found that this functionality was difficult to implement accurately in system designs, and was not greatly useful. As a result, the TSCLKCHANGE functionality and the 'R' bit were removed from the ETMv4.0 specification.

The separate trace components included in some Microcontroller profile processors also implement the same clock change signaling capability. Processors in the Microcontroller profile conform to a specific version of the Arm architecture that is defined in the Arm Architecture Reference Manuals:

  • Arm®v6-M Architecture Reference Manual

  • Arm®v7-M Architecture Reference Manual

  • Arm®v8-M Architecture Reference Manual

ARMv6-M does not support trace, and therefore does not support trace timestamping.

ARMv7-M supports packet generation from the ITM. (The ITM also generates trace packets on behalf of the DWT.) The Global timestamp packet format 1 (GTS1) packet includes a ClkCh bit to indicate a clock change. Therefore, processors that implement the ARMv7-M architecture and include an ITM must support TSCLKCHANGE functionality.

The Armv8-M architecture retains the same ITM GTS1 format as ARMv7-M, and includes the TSCLKCHANGE functionality for backwards compatibility. However, the ITM is supported only in the Mainline extension of Armv8-M, so is not included in any Baseline implementation.

For any processor whose ETM conforms to ETMv3.5, TSCLKCHANGE functionality is required for the ETM.

For Cortex-M processors:


  • Cortex-M0, Cortex-M0+, Cortex-M1: No trace is supported, therefore no TSCLKCHANGE functionality.


  • Cortex-M3, Cortex-M4: ITM supports ClkCh function. ETM conforms to ETMv3.5.

  • Cortex-M7: ITM supports ClkCh. ETM conforms to ETMv4.


  • Cortex-M23: Baseline implementation does not support ITM. ETM conforms to ETMv3.5

  • Cortex-M33: Mainline extension supports ITM with ClkCh. ETM conforms to ETMv4.





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